System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor

A semiconductor device comprising:

• a clock generating circuit for generating an internal clock on the basis of a received clock;
• an input buffer circuit for receiving an input signal applied thereto from an external source;
• and
• an input circuit for retrieving and outputting said input signal in synchronism with said internal clock supplied from said clock generating circuit;
• wherein said input circuit includes:
• a delay circuit with a selectable delay amount for delaying an output of said input buffer circuit;
• an input circuit portion for retrieving the output of said input buffer circuit in synchronism with said internal clock;
• a phase judge circuit for judging a phase of the output of said input buffer circuit with respect to said internal clock by judging an output signal value of said input circuit portion;
• and
• a delay control circuit for controlling the delay amount of said delay circuit in such a manner that the output of said input buffer circuit has a predetermined phase relation with respect to said internal clock, on the basis of the result of judgement at said phase judge circuit.

A semiconductor device system comprising a plurality of semiconductor devices operating in synchronism with a clock and means for transmitting signals between said semiconductor devices, said semiconductor devices including a driving-end semiconductor device for producing said clock and an output signal in synchronism with said clock and a receiving-end semiconductor device for retrieving as an input signal said output signal produced from said driving-end semiconductor device in synchronism with said clock received;

• said semiconductor device system operating in one of operation modes including a normal mode and a receiving timing adjust mode for adjusting a timing of retrieving said input signal at said receiving-end semiconductor device;
• wherein said driving-end semiconductor device produces said output signal of a predetermined pattern during said receiving timing adjust mode;
• wherein said receiving-end semiconductor device includes a clock generating circuit for generating an internal clock on the basis of said received clock, a plurality of input circuits for retrieving and producing input signals in synchronism with said internal clock supplied thereto from said clock generating circuit, and an inter-signal timing adjusting circuit for detecting a phase difference between output signals of said input circuits and adjusting said output signals into the same phase;
• wherein each of said input circuits includes an input timing adjusting circuit for adjusting the retrieving timing of the input signal;
• and
• wherein said inter-signal timing adjusting circuit and said input timing adjusting circuit change the delay amount during said receiving timing adjust mode and holds the delay amount during said normal mode.

A semiconductor device comprising:

• a clock generating circuit for generating an internal clock on the basis of an external clock applied thereto from an external source;
• a signal input circuit for receiving an input signal applied thereto in synchronism with said external clock and retrieving said input signal into said semiconductor device in synchronism with the internal clock generated by said clock generating circuit;
• and
• a dummy input circuit supplied with a signal in synchronism with said input signal having the same frequency as said external clock for judging as output signal value at a time of retrieving said input signal in synchronism with the internal clock generated by said clock generating circuit thereby to judge whether a timing of retrieving said input signal of said signal input circuit is advanced or delayed with respect to said internal clock;
• wherein said clock generating circuit includes a delay circuit for selectively delaying said external clock applied thereto and generating said internal clock on the basis of the result of judgement at said dummy input circuit, and a delay control circuit for controlling the delay amount of said delay circuit on the basis of the result of judgement at said dummy input circuit.