Integrated circuit memory devices that utilize data masking techniques to facilitate test mode analysis

An integrated circuit memory device, comprising:

• a memory cell array;
• a mask signal generator that generates first and second internal data masking signals, in response to at least one single data rate mode signal;
• and
• a data controller that passes input data to said memory cell array when the first and second internal data masking signals are inactive and masks at least a portion of the input data from said memory cell array when one of the first and second internal data masking signals is active;
• and
• wherein said mask signal generator is responsive to first and second single data rate mode signals and comprises a buffer having a data input that receives an external data strobe signal and a control input that receives one of the first and second single data rate mode signals.

A double data rate synchronous DRAM device, comprising:

• a memory cell array;
• a mask signal generator that generates an internal data masking signal during a test mode of operation;
• and
• a data controller that passes input data to said memory cell array when the internal data masking signal is inactive and masks at least a portion of the input data from said memory cell array when the internal data masking signal is active therefor.