Integrated circuit memory devices having programmable latency periods and methods of operating same

An integrated circuit memory device, comprising:

• a column select signal generator which generates a column select signal pulse having leading and trailing edges;
• a memory cell array;
• a first sense amplifier electrically coupled to said memory cell array and responsive to the column select signal pulse;
• an input/output gate electrically coupled to said first sense amplifier;
• a first internal clock generator which generates a first internal clock signal in response to an external clock signal;
• a write enable buffer which is responsive to a write enable signal and the first internal clock signal and generates a write state signal;
• a second internal clock generator which generates a second internal clock signal in response to the write state signal, the first internal clock signal and at least one latency state signal;
• a second sense amplifier electrically coupled to said input/output gate and responsive to the second internal clock signal;
• and
• a controller, electrically coupled to said column select signal generator and responsive to the at least one latency state signal, which adjusts the timing of at least one of the leading and trailing edges of the column select signal pulse as a function of the value of the at least one latency state signal;
• wherein said controller is responsive to the first internal clock signal and the write state signal and generates first and second control signals;
• wherein said column select signal generator is responsive to the first and second control signals;
• wherein the first control signal is delayed relative to the first internal clock signal by a first delay;
• wherein the second control signal is delayed relative to the first internal clock signal by a second delay which is less than the first delay;
• and wherein said controller adjusts the timing of at least one of the leading and trailing edges of the column select signal pulse by adjusting the values of the first and second delays as a function of the value of the at least one latency state signal.

A method of operating an integrated circuit memory device, comprising the steps of:

• generating a latency control signal;
• generating a first internal clock signal;
• generating first and second control signals as first and second pulse trains, respectively, which are in-sync with the first internal clock signal, if the latency control signal is in a first logic state;
• switching the latency control signal from the first logic state to a second logic state opposite the first logic state;
• delaying the first and second pulse trains in time relative to the first internal clock signal, in response to said step of switching the latency control signal;
• and
• generating a column select signal as a third pulse train which has leading edges in-sync with the inactive-to-active transitions associated with the first pulse train and trailing edges in-sync with the inactive-to-active transitions associated with the second pulse train.