Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

A semiconductor memory device for taking an external signal in synchronization with a clock signal applied in the form of a pulse, comprising:

• a DRAM array including a plurality of dynamic memory cells arranged in a matrix of rows and columns;
• an SRAM array including a plurality of static memory cells arranged in a matrix of rows and columns;
• data transfer means for transferring data at least between a selected memory cell of said DRAM array and a selected memory cell of said SRAM array;
• command register means for storing command data for setting a special operation mode of said semiconductor memory device and arrangement of data input and output pins of said semiconductor memory device;
• and
• writing means responsive to said clock signal for storing a prescribed number of bits of an address for selecting a column of said DRAM array, in said command register means as the command data.

A semiconductor memory device for taking an external signal in synchronization with a clock signal applied in the form of a pulse, comprising:

• a DRAM array including a plurality of dynamic memory cells arranged in a matrix of rows and columns;
• an SRAM array including a plurality of static memory cells arranged in a matrix of rows and columns;
• data transfer means for carrying out at least data transfer between a selected memory cell in said DRAM array and a selected memory cell in said SRAM array;
• command register means for storing command data for designating at least a special operation mode of said semiconductor memory device;
• and
• means responsive to a combination of external control signal states applied in synchronization with said clock signal, taking in signal currently applied to address input nodes receiving an address for selecting a row and a column of said DRAM array as command data, and taking a part of the currently applied signals as data for designating a type of data transfer mode to said DRAM array of said data transfer means and as data for designating a test mode of said semiconductor memory device, for storing the data in said command register means.

A synchronous type semiconductor device inputting an external signal in synchronization with an external clock signal, comprising:

• a first transistor element connected between a first supply node and an output node and for driving said output node to a potential level of the first supply node in response to a drive signal;
• a second transistor element connected between said output node and a second supply node for driving said output node to a potential level of the second supply node;
• and
• control means responsive to inactivation of said drive signal for activating said second transistor element for a predetermined time period from a transition to a first logic state of said external clock signal.

A synchronous type semiconductor memory device taking a plurality of external signals in synchronization with a clock signal and capable of a prescribed test mode operation, comprising:

• detecting means for detecting, in synchronization with said clock signal, application of a combination of prescribed states of said plurality of external signals continuously twice or more;
• test mode setting means responsive to a detection signal from said detecting means for taking a prescribed address signal bit, and setting a test mode so that a synchronous type semiconductor memory device is set to a state permitting said test mode operation;
• and
• means for resetting, when a combination of prescribed states of said plurality of external signals is applied after detection by said detecting means, said test mode setting means.

A synchronous type semiconductor memory device including memory cells, comprising:

• a signal terminal;
• timer means for generating a refresh request at a prescribed time interval;
• mode setting means responsive to a mode setting signal for setting transmission of the refresh request from said timer means to said signal terminal to an inhibition or a permission state;
• and
• refresh means coupled to said signal terminal and responsive to the refresh request applied to said signal terminal, for executing refreshing of said memory cells.

An image processing system comprising:

• data processing unit generating an access request in synchronization with a first clock signal;
• a clock synchronized type semiconductor memory device operating in a registered output mode in which an address signal is applied in synchronization with a second clock signal and data of a selected memory cell designated by the address signal is registered for a cycle of said second clock signal for external outputting;
• video processing unit for displaying an image;
• and
• access control means for allowing said data processing unit and said video processing unit to access said clock synchronized type semiconductor memory device alternately.