Memory device with decoder having simplified structure
AssigneeNEC Corporation
InventorShyuichi Tsukada
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device include a memory cell plate and a plurality of decoders. The memory cell plate includes a plurality of memory cells arranged in a matrix of rows and columns. Each of the plurality of decoders includes a series connection of at least two MOS transistors. One of two nodes of the series connection is connected to a state signal which is associated with one of the columns, and which is not activated in an active mode. Also, gate control signals are generated by predecoding a part of an address signal and supplied to gates of the at least two MOS transistors, respectively, whereby one of the rows is selected based on a potential of the other node of the series connection. The state signal may be a bit line precharge signal.
Claims22
A semiconductor memory device comprising:
- a memory cell plate including a plurality of memory cells arranged in a matrix of rows and columns;
- a precharging circuit connected between a first memory cell of said plurality of memory cells and a sense amplifier to precharge a bit line of said memory cell;
- a plurality of decoders, each of which includes a series connection of at least two MOS transistors,
- wherein a first node of said series connection is connected to a state signal which is associated with one of said columns, and which is not activated in an active mode, and
- wherein gate control signals derived from a predecoded part of an address signal are supplied to gates of said at least two MOS transistors, respectively, to select a row of said matrix of rows based on a potential of a second node of said series connection.
A dynamic random access memory (DRAM) comprising:
- a memory cell plate, which includes a plurality of memory cells arranged in a matrix of rows and columns;
- a plurality of predecoders decoding an address signal to produce predecoded signals;
- a group of decoders, each of which decodes a part of said predecoded signals to select one of said rows of said memory cells of said memory cell plate, wherein each of said decoders includes a series connection of at least two MOS transistors, wherein one of two nodes of said series connection is connected to a bit line precharge signal which is associated with one of said columns of said memory cells, and which is not activated in an active mode, wherein said part of said predecoded signals is supplied to gates of said at least two MOS transistors, respectively, whereby one of said rows is selected based on a potential of the other node of said series connection;
- a precharging section precharging bit lines of said columns of said memory cells in each of said plurality of memory cell plates in response to said bit line precharge signal;
- and
- a sense amplifier section, wherein said sense amplifier section senses a data from one of said memory cells which is specified by said selected row of said memory cells.
A semiconductor memory device comprising:
- a memory cell plate including a plurality of memory cells arranged in a matrix of rows and columns;
- a plurality of predecoders decoding an address signal to produce a plurality of predecoded signals;
- a precharge control circuit generating a bit line precharge signal from one of said predecoded signals;
- a plurality of decoders, each of which decodes a part of said plurality of predecoded signals other than said one predecoded signal and said bit line precharge signal to produce a plurality of decoded signals;
- a plurality of word drivers provided for said plurality of decoders, and driving rows of memory cells of said memory cell plate based on a remaining part of said plurality of predecoded signals other than said one predecoded signal and said part of said plurality of predecoded signals and said plurality of decoded signals, respectively.
Dependencies are inferred from the claim text.