Asynchronous multiport register file with self resetting write operation

Abstract

Self-reset and write control circuits for high performance asynchronous multiport register files are disclosed. The high speed write operation is achieved by the combination of static data input and dynamic data control circuits. The write timing signal generation, true and complement address buffer, decoder and wordline drivers, and write enable circuits employ the advantages of a fully custom designed methodology with self-resetting complementary metal oxide semiconductor (SRCMOS) circuit techniques. Individual write enable pulses applied to respective input ports of a multiport register cell are effective to establish a priority among those input ports. In this design, the priority of the B-write-port over the A-write-port is established when both write ports address the same register. The present invention provides an effective input isolation/decoupling circuit technique which allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in effective input isolation scheme.

Dependencies are inferred from the claim text.