Memory device having direct sense circuit

A semiconductor device including a memory circuit comprising:

• a plurality of memory blocks to be activated independently to each other, each memory block having memory cells arranged in rows and columns and including a bit line coupled to a plurality of memory cells;
• a direct sense circuit coupled between a read-data bus line and said bit line, said direct sense circuit being activated with activating a direct-sense driving line;
• a control circuit for generating a read signal activated for a predetermined time in response to a read command;
• and
• a direct-sense activation circuit for activating said direct-sense driving line in response to said activated read signal when a corresponding one of said memory blocks is activated,
• wherein said direct sense circuit comprise:
• a column gate having a control input and a current path, said control input thereof being coupled to a column selection line;
• and
• a direct sense gate having a control input and a current path, said control input thereof being coupled to said bit line,
• wherein said current paths of said column gate and said direct sense gate are coupled in series between said direct-sense driving line and said read-data bus line.