Current detection type sense amplifier

A sense amplifier of the current detection type as claimed, comprising:

• a pair of common data lines connected through MOS transistors to pairs of bit lines, to which data of memory cells of said static type RAM are connected;
• a pair of bipolar transistors whose emitter terminals are connected to said data lines;
• a first power supply connected through resistors to collector terminals of said bipolar transistors, which serve as signal output terminals of said sense amplifier;
• a second power supply connected to base terminals of said bipolar transistors;
• a pair of resistance elements connected to emitter terminals of said bipolar transistors for normally supplying current to said sense amplifier therefrom;
• and
• a potential stabilization circuit connected to each of said pairs of bit lines for said memory cells and including a pair of bipolar transistors whose emitter terminals are connected to said bit lines and whose base terminals are connected to a first control circuit while collector terminals of said bipolar transistors are connected to a third power supply, said bit lines being connected to each other by said MOS transistors while gate electrodes of said MOS transistors are connected to a second control circuit, whereby, when the memory cells connected to the pair of bit lines are not selected, said MOS transistors exhibit a conducting state to make the bit lines have an equal potential, and a base potential to said base terminals of said bipolar transistors is determined so as to be equal to a potential of said data lines.

A sense amplifier of the current detection type for a static type RAM, comprising:

• a pair of common data lines connected through MOS transistors to pairs of bit lines, to which data of memory cells of said static type RAM are connected;
• a pair of bipolar transistors whose emitter terminals are connected to said data lines;
• a first power supply connected through resistors to collector terminals of said bipolar transistors, which serve as signal output terminals of said sense amplifier;
• a second power supply connected to base terminals of said bipolar transistors;
• a pair of constant current sources connected to emitter terminals of said bipolar transistors for normally supplying current to said sense amplifier therefrom;
• and
• a potential stabilization circuit connected to each of said pairs of bit lines for said memory cells and including a pair of bipolar transistors whose emitter terminals are connected to said bit lines and whose base terminals are connected to a control circuit while collector terminals of said bipolar transistors are connected to a third power supply, whereby, when the memory cells connected to the bit lines are not selected, a base potential to said base terminals of said bipolar transistors is determined so as to be equal to a potential of said data lines.

A sense amplifier of the current detection type for a static type RAM, comprising:

• a pair of common data lines connected through MOS transistors to pairs of bit lines, to which data of memory cells of said static type RAM are connected;
• a pair of bipolar transistors whose emitter terminals are connected to said data lines;
• a first power supply connected through resistors to collector terminals of said bipolar transistors, which serve as signal output terminals of said sense amplifier;
• a second power supply connected to base terminals of said bipolar transistors;
• a pair of constant current sources connected to emitter terminals of said bipolar transistors for normally supplying current to said sense amplifier therefrom;
• and
• a potential stabilization circuit connected to each of said pairs of bit lines for said memory cells and including a pair of bipolar transistors whose emitter terminals are connected to said bit lines and whose base terminals are connected to a first control circuit while collector terminals of said bipolar transistors are connected to a third power supply, said bit lines being connected to each other by said MOS transistors while gate electrodes of said MOS transistors are connected to a second control circuit, whereby, when the memory cells connected to the pair of bit lines are not selected, said MOS transistors exhibit a conducting state to make the bit lines have an equal potential, and a base potential to said base terminals of said bipolar transistors is determined so as to be equal to a potential of said data lines.