Semiconductor integrated circuit device
AssigneeNEC Corporation
InventorsTaketo Maesako, Kouki Yamamoto, Yoshinori Matsui, Kenichi Sakakibara
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Abstract
A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.
Claims23
A semiconductor memory device comprising:
- a main memory unit;
- a sub memory unit including a plurality of memory portions;
- a data input/output circuit interfacing with an outside of said memory device, each of said memory portions having a first data port and a second data port provided independently of said first data port,
- a first data transfer line coupled between said main memory unit and said first data port;
- and
- a second data transfer line different from said first data transfer line coupled between said second data port and said data input/output circuit, said first data port of each of said memory portions being coupled to said main memory unit via said first data transfer line and said second data port of each of said memory portions being coupled to said data input/output circuit via said second data transfer line.
A semiconductor memory device comprising:
- a main memory unit;
- a sub memory unit including a plurality of memory portions, each of said memory portions having a first data port and a second data port provided independently of said first data port;
- a data input/output circuit interfacing with an outside of said memory device;
- a first data transfer line coupled between said main memory unit and said first data port so that each of said memory portions is electrically coupled to said main memory unit via said first data transfer line and said first data port;
- and
- a second data transfer line different from said first data transfer line coupled between said second data port and said input/output circuit so that each of said memory portions is electrically coupled to said data input/output circuit via said second data transfer line and said second data port, thereby allowing a data transfer between said main memory unit and a selected first one of said memory portions to be performed in parallel to executing a data transfer between a selected second one of said memory portions and said data input/output circuit.
A semiconductor memory device comprising:
- a first memory unit;
- a second memory unit including a plurality of memory portions, each of said memory portions having a first data port and a second data port;
- a first data transfer line coupled between said first memory unit and said first data port;
- and
- a second data transfer line coupled between said second data port and a data input/output circuit interfacing externally to said memory device.
Dependencies are inferred from the claim text.