Nonvolatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsShigeru Atsumi, Sumio Tanaka
Life of this patent
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Abstract
In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.
Claims17
A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate having a P-type conductivity region;
- a stacked gate memory cell having a control gate, a charge storing layer, a source, and a drain, said stacked gate memory cell being formed in said semiconductor substrate;
- a word line connected to the control gate of said stacked gate memory cell;
- a word line potential providing circuit for providing a boosted potential greater than a positive power supply potential to said word line in a data write mode, to cause electrons to be charged into the charge storing layer by a hot electron injection, and for providing a negative potential to said word line in a data erase mode, to cause the electrons stored in the charge storing layer to be discharged into said semiconductor substrate;
- a drain potential providing circuit for providing a positive potential to the drain of said stacked gate memory cell in the data write mode, to cause the electrons to be charged into the charge storing layer by the hot electron injection;
- and
- a substrate potential providing circuit for providing a boosted potential greater than the positive power supply potential to said semiconductor substrate in the data erase mode, to cause the electrons stored in the charge storing layer to be discharged into said semiconductor substrate.
A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate having a P-type conductivity region;
- a stacked gate memory cell having a control gate, a charge storing layer, a source, and a drain, said stacked gate memory cell being formed in said semiconductor substrate;
- a word line connected to the control gate of said stacked gate memory cell;
- a word line potential providing circuit for providing a boosted potential greater than a positive power supply potential to said word line in a data write mode, to cause electrons to be charged into the charge storing layer by a hot electron injection;
- a drain potential providing circuit for providing a positive potential to the drain of said stacked gate memory cell in the data write mode, to cause the electrons to be charged into the charge storing layer by the hot electron injection;
- a source potential providing circuit connected to the source;
- and
- a substrate potential providing circuit for providing a boosted potential greater than the positive power supply potential to said semiconductor substrate in a data erase mode, to cause the electrons stored in the charge storing layer to be discharged into said semiconductor substrate.
Dependencies are inferred from the claim text.