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US 6,151,250 AGranted
Flash memory device and verify method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsKi-Hwan Choi, Jong-Min Park
Life of this patent
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Abstract
A word line voltage supply circuit for a nonvolatile semiconductor memory device reduces power supply noise by deactivating a high voltage generator during a verify sensing operation. The word line voltage supply circuit includes a high voltage generator that produces a high voltage signal in response to a control signal from a controller. A voltage regulator regulates the high voltage signal to generate a verify voltage signal that is applied to a selected memory cell. The controller deactivates the control signal during a verify sensing operation so as to eliminate power supply noise caused by the pumping operation of the high voltage generator.
Claims11
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns;
- a high voltage generator for generating a high voltage signal in response to a control signal;
- a voltage regulator coupled to the high voltage generator for regulating the high voltage signal to produce a verify voltage signal which is applied to a selected row;
- and
- a controller coupled to the high voltage generator for generating the control signal, wherein the controller deactivates the control signal responsive to a sense enable signal during a verify sensing operation, thereby deactivating the high voltage generator.
2 more elements
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns;
- a high voltage generator for generating a high voltage signal in response to a control signal;
- a voltage regulator coupled to the high voltage generator for regulating the high voltage signal to produce a verify voltage signal which is applied to a selected row;
- and
- a controller coupled to the high voltage generator for generating the control signal, wherein the controller deactivates the control signal during a verify sensing operation, thereby deactivating the high voltage generator;
- wherein the controller comprises:
- an invertor having an input terminal for receiving a verify enable signal;
- and
- a NOR gate having one input terminal connected to an output terminal of the invertor and another input terminal for receiving a sense enable signal.
6 more elements
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a plurality of word lines, a plurality of bit lines and a plurality of memory cells arranged at intersections of the word lines and the bit lines;
- a row selector coupled to the memory cell array for selecting one of the word lines in response to a row address;
- a column selector coupled to the memory cell array for selecting one of the bit lines in response to a column address;
- a sense amplifier coupled to the column selector for sensing data in a memory cell accessed by the selected word line and bit line in response to a sense enable signal;
- and
- a word line voltage supply circuit coupled to the row selector for generating a verify voltage signal, wherein the word line voltage supply circuit includes a high voltage generator, and wherein the word line voltage supply circuit disables the high voltage generator during a verify sensing operation;
- and
- wherein the word line voltage supply circuit further includes:
- a voltage regulator coupled to the high voltage generator for generating a verify voltage signal responsive to the high voltage signal;
- a switching circuit coupled between the voltage regulator and the row selector for transferring the verify voltage signal to the row selector;
- and
- a controller coupled to the high voltage generator for deactivating the high voltage generator responsive to a sense enable signal.
9 more elements
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a plurality of word lines, a plurality of bit lines and a plurality of memory cells arranged at intersections of the word lines and the bit lines;
- a row selector coupled to the memory cell array for selecting one of the word lines in response to a row address;
- a column selector coupled to the memory cell array for selecting one of the bit lines in response to a column address;
- a sense amplifier coupled to the column selector for sensing data in a memory cell accessed by the selected word line and bit line in response to a sense enable signal;
- and
- a word line voltage supply circuit coupled to the row selector for generating a verify voltage signal, wherein the word line voltage supply circuit includes a high voltage generator, and wherein the word line voltage supply circuit disables the high voltage generator during a verify sensing operation;
- wherein the word line voltage supply circuit further includes:
- a voltage regulator coupled to the high voltage generator for generating a verify voltage signal responsive to the high voltage signal;
- a switching circuit coupled between the voltage regulator and the row selector for transferring the verify voltage signal to the row selector;
- and
- a controller coupled to the high voltage generator for deactivating the high voltage generator responsive to a sense enable signal;
- and
- wherein the controller comprises:
- an invertor having an input terminal of receiving a verify enable signal;
- and
- a NOR gate having one input terminal connected to an output terminal of the invertor and another input terminal for receiving the sense enable signal.
13 more elements
A method for performing a verify operation in a nonvolatile memory device having an array of memory cells for storing data and a high voltage generator for generating a high voltage signal, the method comprising:
- activating the high voltage generator in response to a verify enable signal;
- regulating the high voltage signal to generate a verify voltage signal;
- and
- deactivating the high voltage generator responsive to a sense enable signal during a verify sensing operation.
1 more element
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns;
- means for generating a high voltage signal;
- means for regulating the high voltage signal to produce a verify voltage signal which is applied to a selected row;
- and
- means for deactivating the means for generating a high voltage signal during a verify sensing operation.
2 more elements
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns;
- means for generating a high voltage signal;
- means for regulating the high voltage signal to produce a verify voltage signal which is applied to a selected row;
- and
- means for deactivating the means for generating a high voltage signal during a verify sensing operation;
- wherein the means for deactivating the means for generating a high voltage signal includes:
- an invertor having an input terminal for receiving a verify enable signal;
- and
- a NOR gate having one input terminal connected to an output terminal of the invertor and another input terminal for receiving a sense enable signal.
6 more elements
Dependencies are inferred from the claim text.