US 6,151,249 AGranted

NAND-type EEPROM having bit lines and source lines commonly coupled through enhancement and depletion transistors

AssigneeKabushiki Kaisha Toshiba

InventorsRiichiro Shirota, Masaki Momodomi

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Abstract

In an EEPROM including a plurality of NAND memory cells each constituted by connecting memory cells each having a floating gate and a control gate in series with each other, first selection transistors respectively coupled between the same bit line and terminals, on one side, of each pair constituted by two NAND memory cells of the plurality of memory cells, and second selection transistors respectively coupled between terminals on the other side and source lines (SL), the first or second selection transistors are constituted by an enhancement transistor and a depletion transistor which are coupled in series with each other, and the arrangements of the depletion transistor and enhancement transistor of the first selection transistors are reversed to those of the second selection transistors in the same NAND memory cells.

Claims16

Dependent claims

A nonvolatile semiconductor memory device comprising:

a plurality of NAND memory cells each having first and second terminals and constituted by connecting a plurality of memory cells each having a control gate in series with each other, said NAND memory cells including adjacent first and second NAND memory cells;
bit lines commonly used for NAND memory sets each constituted by at least said first and second NAND memory cells of said NAND memory cells, said bit lines being coupled to the first terminals of said NAND memory cells;
source lines commonly used for the NAND memory sets each constituted by at least said first and second NAND memory cells of said NAND memory cells, said source lines being coupled to the second terminals of said NAND memory cells;
first selection transistors arranged between the first terminal of the first NAND memory cell and said bit line;
second selection transistors arranged between the first terminal of said second NAND memory cell and said bit line;
third selection transistors arranged between the second terminal of the first NAND memory cell and said source line;
fourth selection transistors arranged between the second terminal of said second NAND memory cell and said source line;
a first control gate line coupled to at least control gates of said first selection transistors;
a second control gate line coupled to at least control gates of said second selection transistors;
a third control gate line coupled to at least control gates of said third selection transistors;
a fourth control gate line coupled to at least control gates of said fourth selection transistors.

8 more elements

A nonvolatile semiconductor memory device comprising:

a plurality of NAND memory cells each having first and second terminals and constituted by connecting a plurality of memory cells each having a control gate in series with each other, said NAND memory cells including adjacent first and second NAND memory cells;
bit lines commonly used for NAND memory sets each constituted by at least said first and second NAND memory cells of said NAND memory cells, said bit lines being coupled to the first terminals of said NAND memory cells connected in series;
source lines commonly used for the NAND memory sets each constituted by at least said first and second NAND memory cells of said NAND memory cells, said source lines being coupled to the second terminals of said NAND memory cells connected in series;
first selecting means arranged between the first terminals of said first and second NAND memory cells and said bit line;
and
second selecting means arranged between the second terminals of said first and second NAND memory cells and said source line;
wherein said first selecting means include enhancement transistors and depletion transistors which are coupled in series with each other, and an order of connection of said enhancement transistors and said depletion transistors to the first terminals of said first and second NAND memory cells are reversed to each other, and
said second selecting means include enhancement transistors and depletion transistors which are coupled in series with each other, and an order of connection of said enhancement transistors and said depletion transistors to the second terminals of said first and second NAND memory cells are reversed to each other.

5 more elements

Dependencies are inferred from the claim text.