Dual floating gate EEPROM cell array with steering gates shared by adjacent cells

An array of non-volatile memory cells on a semiconductor substrate, comprising:

• elongated source and drain diffusions being spaced apart in a first direction across the substrate and having lengths extending in the second direction across the substrate, said first and second directions being orthogonal with each other,
• a plurality of memory cells organized in a plurality of rows that extend in the first direction across the substrate and are spaced apart in the second direction, said memory cells individually including floating gates capacitively coupled with the substrate through gate dielectric layers over first and second channel regions positioned adjacent opposing diffusions with a third channel region therebetween,
• a plurality of elongated steering gates having lengths extending in the second direction, said steering gates being individually positioned in the first direction to overlay adjacent floating gates of adjacent memory cells and a diffusion therebetween, and having spaces therebetween in the first direction that includes the third channel region, and
• a plurality of elongated select gates having lengths extending in the first direction along the rows of memory cells and being capacitively coupled with the substrate in the third channel region.

A non-volatile memory cell formed on a semiconductor substrate, comprising:

• source and drain diffusions in a surface of the substrate that are spaced apart to form a channel having three non-overlapping regions extending in a given direction therebetween,
• a first floating gate positioned over a first of the channel regions and extending in said given direction a part way over an adjacent source diffusion with a first floating gate dielectric layer area positioned between the first floating gate and the substrate surface,
• a second floating gate positioned over a second of the channel regions and extending in said given direction a part way over an adjacent drain diffusion with a second floating gate dielectric layer area positioned between the second floating gate and the substrate surface,
• a first steering gate positioned over the first floating gate and extending in said given direction over the source diffusion and an edge of the first floating gate adjacent the source diffusion but not over an edge of the first floating gate adjacent the third channel region, said first steering gate being separated from the first floating gate and the source diffusion by a first steering gate dielectric layer,
• a second steering gate positioned over the second floating gate and extending in said given direction over the drain diffusion and an edge of the second floating gate adjacent the drain diffusion but not over an edge of the second floating gate adjacent the third channel region, said second steering gate being separated from the second floating gate and the drain diffusion by a second steering gate dielectric layer,
• a select gate positioned over a third of the channel regions in between the first and second channel regions with a first select gate dielectric layer area positioned between the select gate and the substrate surface, said select gate being coupled with the edges of the first and second floating gates adjacent the third channel region through respective layers of tunnel dielectric positioned therebetween, thereby allowing the floating gates to be erased to the select gate, said select gate additionally extending over the first and second steering gates with respective second and third layers of select gate dielectric positioned therebetween.

A non-volatile memory cell structure, comprising:

• a semiconductor substrate having an outer surface,
• a plurality of trenches spaced apart in a given direction across said outer surface, said trenches individually having a cross-section in said given direction that extends into the outer surface with opposing substrate sides and a bottom substrate surface, said trenches individually including:
• a diffusion in the substrate at the bottom the trench,
• a pair of floating gates positioned along the opposing substrate sides of the trench with floating gate dielectric therebetween and extending out of the trenches to terminate in said given direction with edges on the outer substrate surface on opposite sides of the trench, individual pairs of floating gates being separated a space in said given direction over the diffusion, and
• a single steering gate positioned between the floating gates and capacitively coupled therewith through steering gate dielectric layers on opposite sides of the steering gate in said given direction, and
• a plurality of select gates capacitively coupled through select gate dielectric layers to the substrate outer surface adjacent said floating gate edges.

A non-volatile memory system, comprising:

• an array of memory cells on a semiconductor substrate, said array including:
• elongated source and drain diffusions being spaced apart in a first direction across the substrate and having lengths extending in the second direction across the substrate, said first and second directions being orthogonal with each other,
• a plurality of memory cells organized in a plurality of rows that extend in the first direction across the substrate and are spaced apart in the second direction, said memory cells individually including floating gates capacitively coupled with the substrate through gate dielectric layers over first and second channel regions positioned adjacent opposing diffusions with a third channel region therebetween,
• a plurality of elongated steering gates having lengths extending in the second direction, said steering gates being individually positioned in the first direction to overlay adjacent floating gates of adjacent memory cells and a diffusion therebetween, and having spaces therebetween in the first direction that includes the third channel region, and
• a plurality of elongated select gates having lengths extending in the first direction along the rows of memory cells and being capacitively coupled with the substrate in the third channel region, and
• a word line decoding and voltage supply circuit connected to drive the select gates of the memory cells of individual rows to at least a first word line voltage level that prevents current from flowing through the third channel region of the memory cells in unselected rows and a second word line voltage level that allows current to flow through the third channel region of the memory cells of the selected rows,
• a steering gate decoding and voltage supply circuit connected to individually drive selected steering gates to at least one first steering gate voltage level that renders conductive the first channel region of one memory cell and the second channel region of an adjacent memory cell for an operating range of levels of charge carried by the floating gate s that are respectively capacitively coupled therewith, at least one second steering gate voltage level for reading a state of the floating gate capacitively coupled with the first channel region of one memory cell or the floating gate capacitively coupled with the second channel region of an adjacent memory cell, and at least one third steering gate voltage level for programming a state of the floating gate capacitively coupled with the first channel region of one memory cell or the floating gate capacitively coupled with the second channel region of an adjacent memory cell, and
• a bit line decoding and voltage supply circuit connected to drive the source and drain diffusions of individual columns of cells to at least a first condition wherein the source and drain diffusions of a column of memory cells selected for reading or writing have unequal voltages and a second condition wherein the source and drain diffusions of a column of memory cells not selected for reading, or writing have equal voltages.