US 6,151,244 AGranted

Dynamic semiconductor memory device

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsTakeshi Fujino, Kazutami Arimoto

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Abstract

Memory cell minimum units (MCU) formed of multi-bit one transistor/one capacitor type memory cells are repeatedly arranged in a column direction, and bit line contacts (BCT) are shifted in the column direction relative to a row direction. The bit line contacts are repeatedly shifted with a prescribed number of bit lines as a unit. A set of a read bit line onto which memory cell data are read and a reference bit line supplying a reference potential can be obtained by controlling the voltage of cell plate lines and bit lines for each set of bit lines. Accordingly, a memory cell occupation area can be reduced and sensing operation in the folded bit line arrangement is possible. Consequently, a memory cell occupation area per one bit can be dramatically reduced and sensing operation in the folded bit line arrangement can be performed.

Claims16

Dependent claims

A semiconductor memory device comprising:

a plurality of word lines each arranged extending in a row direction and in parallel to others;
a plurality of first bit lines each arranged extending in a column direction and in parallel to others;
a plurality of one transistor/one capacitor type memory cells arranged corresponding to crossing of said plurality of word lines and said plurality of first bit lines, units of two memory cells arranged repeatedly in the column direction, two memory cells being placed opposite to each other relative to a bit line contact for making a contact with a corresponding first bit line, bit line contacts for adjacent bit lines being periodically positioned differently, and the bit line contacts being periodically positioned in the row direction with a plurality of bit lines being a unit, the bit line contacts and the memory capacitors being arranged in alignment in the row direction with the plurality of bit lines being the unit;
a plurality of cell plate lines individually provided corresponding to the first bit lines and coupled to cell plate nodes of the memory cells on the corresponding first bit lines for transferring cell plate potentials to the cell plate nodes of the memory cells of corresponding first bit lines, the cell plate node being a capacitor electrode of a memory capacitor of the memory cell facing to a data storage node of the memory cell;
and
cell plate potential control circuit coupled to the cell plate lines for individually controlling the cell plate potentials on a cell plate line basis.

3 more elements

A semiconductor memory device comprising:

a plurality of word lines each arranged extending in a row direction and in parallel to others;
a plurality of first bit lines each arranged extending in a column direction and in parallel to others;
a plurality of memory cells arranged corresponding to crossing of said plurality of word lines and said plurality of first bit lines, each memory cell being a one transistor/one capacitor type memory cell, units of two memory cells being placed opposite to each other relative to a bit line contact for making a contact with a corresponding first bit line, bit line contacts for adjacent bit lines being positioned differently and the bit line contacts being periodically positioned in the row direction with a plurality of bit lines being a unit,
wherein the memory cells are arranged such that two memory cells for three of the first bit lines as a unit are arranged in the row direction, two memory cells for three word lines as a unit are arranged in said column direction, and the memory cells are arranged in different patterns between adjacent bit lines and between adjacent word lines;
a plurality of cell plate lines individually provided corresponding to the first bit lines and coupled to cell plate nodes of the memory cells on the corresponding first bit lines for transferring cell plate potentials to the cell plate nodes of the memory cells of corresponding first bit lines, the cell plate node being a capacitor electrode of a memory capacitor of the memory cell facing to a data storage node of the memory cell;
and
cell plate potential control circuit coupled to the cell plate lines for individually controlling the cell plate potentials on a cell plate line basis.

4 more elements

A semiconductor memory device comprising:

a plurality of word lines, each arranged extending in a row direction and in parallel to others;
a plurality of first bit lines, each arranged extending in a column direction and in parallel to others;
a plurality of memory cells arranged corresponding to crossings of said plurality of word lines and said plurality of first bit lines, each memory cell being a one transistor/one capacitor type memory cell, units of two memory cells being placed opposite to each other relative to a bit line contact for making a contact with a corresponding first bit line, bit line contacts for adjacent bit lines being positioned differently, and the bit line contacts being periodically positioned in the row direction with a plurality of bit lines being a unit;
a plurality of first sense amplifiers placed on one side of said plurality of first bit lines, said plurality of first sense amplifiers provided one for three of the first bit lines;
read inhibition circuitry for changing voltages, before a word line selection, to allow memory cell data to be read onto one of two first bit lines connected to memory cells on an addressed row and to inhibit reading of memory cell data onto the other of said two first bit lines in each set formed of the three first bit lines in accordance with a row designation signal, the voltages to be changed being a voltage of said the other of the two first bit lines and a voltage of a cell plate node facing to a data storage node of a memory cell connected to said the other of the two first bit lines;
and
sense amplifier select connect circuitry for connecting said one of the two first bit lines and a remaining first bit line in each set of the first bit lines to a corresponding first sense amplifier in accordance with said row designation signal.

4 more elements

A semiconductor memory device comprising:

a plurality of word lines extending in a row direction and arranged in parallel to each other;
a plurality of first bit lines extending in a column direction and arranged in parallel to each other;
and
a plurality of first NAND type cells arranged in rows and columns each of the first NAND type cells having 2.sup.n one transistor/one capacitor type memory cells connected in series, wherein bit line contacts for contacting the first bit lines to said plurality of first NAND type cells are arranged at the same position in the row direction every first bit lines of a prescribed number of 2.sup.n or 2.multidot.2.sup.n, and the bit line contacts are differently positioned for word lines adjacent to each other and for first bit lines adjacent to each other.

1 more element

Dependencies are inferred from the claim text.