US 6,151,237 A · DRAM having each memory cell storing plural bit data

Abstract

In a dynamic type semiconductor memory device having a classified bit line structure, a feedback capacitor is provided between sub-bit lines and main bit lines of a sub-sense amplifier. A voltage difference read out on the sub-bit lines is transferred to the main bit lines, the read out voltage difference is amplified by a main sense amplifier, and data of superordinate bits is read out. At the same time, the data on said main bit lines is feed-backed to the sub-bit lines through the capacitor. Thereafter, a reading operation from the sub-bit lines to the main bit lines is performed again, thereby enabling a reading operation for data of subordinate bits. Thus, in a dynamic type semiconductor memory device having a conventional memory cell structure, data for two bits can be stored in one memory cell.

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Drawings

Claims6

Dependent claims

A semiconductor memory device comprising:

a main bit line;
a sub-bit line;
a first sense amplifier coupled to said main bit line;
a second sense amplifier coupled to said sub-bit line;
a control transfer gate provided to divide said sub-bit line into a first partial sub-bit line and a second partial sub-bit line;
and
a writing circuit supplying individual voltages to said first and second partial sub-bit lines and thereafter activating said control transfer gate to allow distribution of said individual voltages from a precharge operation for said sub-bit line to the next pre-charge operation for said sub-bit line.

4 more elements

A semiconductor memory device comprising:

a main bit line;
a sub-bit line having a first partial sub-bit line, a second partial sub-bit line, and a third partial sub-bit line;
a memory cell coupled to said first partial sub-bit line;
a sense amplifier coupled to said second partial sub-bit line;
a control transfer gate;
and
a writing circuit supplying individual voltages from said main bit line to said first and second partial sub-bit lines, wherein:
said sense amplifier outputs a second potential to said main bit line based upon a first potential on said sub-b it line that is based on data stored in said memory cell at a first period,
said writing circuit transfers said second potential from said main bit line to said first partial sub-bit line at a second period,
said sense amplifier outputs a fourth potential to said main bit line based upon a third potential on said second partial sub-bit line that is based on said first potential and said second potential at a third period,
said writing circuit transfers said fourth potential from said main bit line to said third partial sub-bit line at a fourth period,
said control transfer gate electrically connects said first partial sub-bit line to said third partial sub-bit line to change a potential of said sub-bit line into a fifth potential based on said second potential and said fourth potential at a fifth period,
said fifth potential is written to said memory cell at a sixth period;
and
said first, second, third, fourth, fifth, and sixth periods are from a precharge operation for said sub-bit line to the next precharge operation for said sub-bit line.

12 more elements

Dependencies are inferred from the claim text.

Description5,441 words

Summary1,281 words

#1. Field of the Invention

#The present invention relates to a semiconductor memory device and, more particularly, to a DRAM (dynamic random access memory) type semiconductor memory device wherein each of dynamic memory cells is constructed to store a plurality of bit data.

#2. Description of the Related Art

Brief description of the drawings13 figures

#The above and other objects, advantages and features of the present invention will be become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

#FIG. 1 is a circuit diagram showing a constitution of a semiconductor memory device of a first embodiment of the present invention;

#FIG. 2 shows input timing waveforms for explaining reading a write operations of the semiconductor memory device of the first embodiment of the present invention;

Detailed description3,846 words

#Referring now to FIG. 1, in a semiconductor memory device of a first embodiment according to the present invention, reference numeral 1 denotes a memory cell in the dynamic type semiconductor memory device; 2, a storage capacitor; 3, a transfer gate; 4, a storage node; and 5, a sub-sense amplifier. Bit lines are classified into main bit lines and sub-bit lines which are in a complementary relationship. One main sense amplifier and a plurality of sub-sense amplifiers (not shown) are connected to a pair of the main bit lines.

#As will be described below in detail, a feedback capacitor 12 is arranged between the sub-bit line /SBL and the main bit line GBL and a feedback capacitor 13 is arranged between the sub-bit line SBL and the main bit line /GBL. A potential difference read out on the sub-bit lines from the selected memory cell is transferred to the main bit lines. The transferred potential difference to the main bit lines is amplified by a main sense amplifier (not shown) so that more significant bit data is first read out. At the same time, data on the main bit lines is feedbacked to the sub-bit lines via the feedback capacitor. Thereafter, the reading operation of the data from the sub-bit lines to the main bit lines is performed again, whereby less significant bit data can be read out. Furthermore, provided is a transfer gate between the sub-bit lines to separate them from each other. A individual voltage is written to the corresponding sub-bit lines located at the transfer gate side. Thereafter, the transfer gate is activated, and the charges are divided whereby four states are written to the memory cell.

#The semiconductor memory device of the first embodiment of the present invention will be described in more detail, by enplaning an operation of the device.

Facts

Application

09/292,665Filed 16 Apr 1999 · continuation

Priority

JP 8-10382229 Mar 1996

Granted

21 Nov 2000

Term ended

20 Mar 2017

Estimated · how

20 years from earliest known nonprovisional domestic filing. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination. Patent term adjustment is unavailable; no adjustment was added.

Classification6 codes

G11C 11/565
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using capacitive charge…
G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 11/4097
Read-write [R-W] circuits: bit-line organisation, e.g. bit-line layout, folded bit lines

DRAM having each memory cell storing plural bit data

Life of this patent

DRAM having each memory cell storing plural bit data

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims6

Description5,441 words

Drawings

Classification6 codes

Life of this patent

Description5,441 words