System for phase-locking a clock to a digital audio signal embedded in a digital video signal

An apparatus for phase-locking a clock to a digital audio signal embedded within a digital video signal comprising:

• means for generating a first reference frequency signal from digital audio signal samples embedded within the digital video signal by dividing the frequency of the digital audio signal samples by a divisor such that the period of the first reference frequency is greater or equal to that of phase jitter present in the digital audio signal samples;
• means for generating a second reference frequency signal from an output audio sample frequency signal, the frequency of the output audio sample frequency signal being equal to the frequency of the digital audio signal samples so that, when divided by the divisor, the frequency of the second reference frequency signal equals that of the first reference frequency signal;
• means for generating from the first and second reference frequency signals a low jitter clock control signal, the low jitter clock control signal been result of rejecting the phase jitter present in the digital audio signal samples;
• and
• means for generating the output audio sample frequency signal from the low jitter clock control signal.

A system for phase-locking a clock to a digital audio signal embedded within a digital video signal comprising:

• an audio extractor, operative for extracting digital audio signal samples from the digital video signal;
• a first frequency divider coupled to receive the digital audio signal samples from the audio extractor, operative for dividing down the frequency of the digital audio signal samples, having a divisor such that the divided down signal has a period greater or equal to that of phase jitter present in the digital audio signal samples;
• a phase detector coupled to receive the divided down signal from the first frequency divider;
• a loop filtering apparatus coupled to receive output from the phase detector, such that the phase jitter present in the digital audio signal samples is rejected and a low jitter clock control signal is produced;
• a VCO coupled to receive the low jitter clock control signal from the loop filter apparatus;
• and
• a second frequency divider with input coupled to output from the VCO and output coupled for input to the phase detector, such frequency divider having a divisor equal to that of the first frequency divider.