R/2R' ladder switch circuit and method for digital-to-analog converter

A circuit for switching a leg of an R/2R' resistive divider network in a digital-to-analog converter to a high reference voltage or a low reference voltage in response to logic information corresponding to a bit of a binary input applied to a digital input of the digital-to-analog converter, comprising:

• (a) a switch circuit including a first MOSFET having a source coupled to a first conductor conducting the low reference voltage and a drain coupled to a conductor of the leg, and a second MOSFET having a source coupled to the conductor of the leg and a drain coupled to a second reference voltage conductor conducting the high reference voltage;
• (b) a first switch control circuit including
• i. a first CMOS inverter coupled between a first power conductor and a second power conductor, and having an input connected to receive the logic information, and an output coupled to the gate of the first MOSFET,
• ii. a first bootstrapped reference voltage source,
• iii. a first bridge circuit including first and second input terminals and first and second output terminals, the first bootstrapped reference voltage source being coupled between the first and second input terminals,
• iv. a first resistor coupled between the second input terminal and the first output terminal, a second resistor coupled between the first output terminal and the first input terminal, a third resistor coupled between the first input terminal and the second output terminal, a fourth resistor coupled between the second output terminal and the second input terminal, and a third MOSFET coupling the fourth resistor to the second input terminal, and
• v. a first operational amplifier having a first input coupled to the first output terminal, a second input coupled to the second output terminal, and an output connected by a second conductor to a gate electrode of the third MOSFET;
• and
• (c) a second switch control circuit including
• i. a second CMOS inverter coupled between a third power conductor and the second power conductor, and having an input connected to receive a complement of the binary bit signal, and an output coupled to the gate of the second MOSFET,
• ii. a second bootstrapped reference voltage source,
• iii. a second bridge circuit including third and fourth input terminals and third and fourth output terminals, the second bootstrapped reference voltage source being coupled between the third and fourth input terminals,
• iv. a fifth resistor coupled between the fourth input terminal and the third output terminal, a sixth resistor coupled between the third output terminal and the third input terminal, a seventh resistor coupled between the third input terminal and the fourth output terminal, an eighth resistor coupled between the fourth output terminal and the fourth input terminal, and a fourth MOSFET coupling the eighth resistor to the fourth input terminal, and
• v. a second operational amplifier having a first input coupled to the third output terminal, a second input coupled to the fourth output terminal, and an output connected by a third conductor to a gate electrode of the fourth MOSFET, wherein the on resistance of each of the first and second switch MOSFETs is equal to R.sub.ONi, and the resistance 2R' is equal to 2R-R.sub.ONi.

A digital-to-analog converter comprising:

• (a) a resistive divider network including a plurality of series resistors each having a resistance R and a plurality of shunt resistors each having a resistance 2R';
• (b) a circuit for switching a shunt resistor of a resistive divider network in a digital-to-analog converter to either of a low reference voltage and a high reference voltage, including
• (1) a first switch MOSFET coupling the low reference voltage to the shunt resistor, and a second switch MOSFET
• i coupling the shunt resistor to the high reference voltage,
• (2) a first switch control circuit including
• i. a first CMOS logic circuit, having an output coupled to a gate of the first switch MOSFET, and
• ii. a first bridge circuit including a first reference resistor and a first control MOSFET both coupled to the low reference voltage, and a first operational amplifier having an output connected to a gate of the first control MOSFET and also coupled by the first CMOS logic circuit to a gate of the first switch MOSFET and operative to equalize the resistances of the first control MOSFET and the first reference resistor so as to adjust the on resistance of the first switch MOSFET to a value proportional to the resistance of the first reference resistor,
• (3) a second switch control circuit including
• i. a second CMOS logic circuit, having an output coupled to a gate of the second switch MOSFET, and
• ii. a second bridge circuit including a second reference resistor and a second control MOSFET, and a second operational amplifier having an output connected to a gate of the second control MOSFET and also coupled by the second CMOS logic circuit to a gate of the second switch MOSFET and operative to equalize the resistances of the second control MOSFET and the second reference resistor so as to adjust the on resistance of the second switch MOSFET to a value proportional to the resistance of the second reference resistor;
• and
• (c) wherein the on resistance of each of the first and second switch MOSFETs is equal to R.sub.ONi, and the resistance 2R' is equal to 2R-R.sub.ONi.