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US 6,150,886 AGranted
Phase locked loop circuit with multiple combinations which each produce a single phase and multiphase clock signals
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakehiko Shimomura
Life of this patent
Estimating the term…
Abstract
A PLL circuit including multiple sets of phase locked loops, each of which has a phase comparator, a charge pump, a low pass filter, as oscillator, a clock generator and a frequency divider. The various oscillators of the multiple sets each have a different oscillation frequency. The clock generator generates a multiphase clock signal from a single phase clock signal generated by the oscillator. The PLL circuit generates multiple single phase clock signals and multiphase clock signals without need to tune the oscillation frequency of the VCOs over a wide range. The noise of the PLL is reduced since each VCO covers a smaller range of oscillation frequencies.
Claims11
A PLL circuit comprising a plurality of combinations, each of said combinations comprising:
- adjusting means for comparing a phase of an external clock signal with a phase of a frequency divided clock signal, and for adjusting a control voltage in accordance with a phase difference between the two signals compared;
- an oscillator for oscillating a single phase clock signal with a frequency corresponding to the control voltage;
- a clock generator connected to said oscillator, said clock generator for generating a multiphase clock signal from said single phase clock signal generated by said oscillator, said multiphase clock signal and said single phase clock signal having a same frequency;
- and
- a frequency divider for dividing a frequency of the single phase clock signal generated by said oscillator to produce the frequency divided clock signal to be supplied to said adjusting means;
- wherein said oscillator in each of said plurality of combinations has a different oscillation frequency.
3 more elements
A PLL circuit comprising:
- first adjusting means for comparing a phase of an external clock signal with a phase of a first frequency divided clock signal, and for adjusting a first control voltage in accordance with a phase difference between the two signals compared;
- a first oscillator for oscillating a first single phase clock signal with a frequency corresponding to the first control voltage;
- a first clock generator connected to said first oscillator, said first clock generator for generating a first multiphase clock signal from said first single phase clock signal generated by said oscillator, said first multiphase clock signal and said first single phase clock signal having a same frequency;
- a first frequency divider for dividing the frequency of the first clock signal generated by said first oscillator to produce the first frequency divided clock signal to be supplied to said first adjusting means;
- second adjusting means for comparing a phase of the first single phase clock signal supplied from said first oscillator with a phase of a second frequency divided clock signal, and for adjusting a second control voltage in accordance with a phase difference between the two signals compared;
- a second oscillator for oscillating a second single phase clock signal with a frequency corresponding to the second control voltage;
- a second clock generator connected to said second oscillator, said second clock generator for generating a second multiphase clock signal from said second single phase clock signal generated by said second oscillator, said second multiphase clock signal and said second single phase clock signal having a same frequency;
- and
- a second frequency divider for dividing the frequency of the second single phase clock signal generated by said second oscillator to produce the second frequency divided clock signal to be supplied to said second adjusting means;
- wherein said first oscillator and said second oscillator have a different oscillation frequency.
7 more elements
A PLL circuit comprising:
- adjusting means for comparing a phase of an external clock signal with a phase of a frequency divided clock signal, and for adjusting a control voltage in accordance with a phase difference between the two signals compared;
- a first oscillator for oscillating a first single phase clock signal with a frequency corresponding to the control voltage;
- a first clock generator connected to said first oscillator, said first clock generator for generating a first multiphase clock signal from said first single phase clock signal generated by said oscillator, said first multiphase clock signal and said first single phase clock signal having a same frequency;
- a second oscillator for oscillating a second single phase clock signal with a frequency corresponding to the control voltage but different from an oscillation frequency of said first oscillator;
- a second clock generator connected to said second oscillator, said second clock generator for generating a second multiphase clock signal from said second single phase clock signal generated by said second oscillator, said second multiphase clock signal and said second single phase clock signal having a same frequency;
- and
- a frequency divider for dividing the frequency of the first single phase clock signal generated by said first oscillator to produce the frequency divided clock signal to be supplied to said adjusting means.
4 more elements
Dependencies are inferred from the claim text.