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US 6,150,878 AGranted
Low voltage device operable with a high voltage supply
AssigneeChip Express (Israel) Ltd.
InventorsUzi Yoeli, Zvi Orbach
Life of this patent
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Abstract
This invention discloses an integrated circuit device including transistors having predetermined upper voltage limits, a multi-layer metal interconnect structure connecting the transistors to each other and to an external voltage source having a voltage in excess of the predetermined upper voltage limits of a first plurality of the transistors, and a voltage reducer connected along the interconnect structure between the external voltage source and the first plurality of the transistors.
Claims22
An integrated circuit arrangement comprising:
- transistors having predetermined upper voltage limits, wherein
- the transistors are connected to each other and to an external voltage source having a voltage in excess of the predetermined upper voltage limits of a first plurality of said transistors, by a multi-layer metal structure;
- and at least one voltage reducer connected along said multi-layer metal structure between said external voltage source and said first plurality of said transistors, wherein:
- said plurality of transistors each comprise a first gate oxide and said voltage reducer transistor comprises a second gate oxide and wherein said second gate oxide is thicker than the first gate oxide, a thickness of said first gate oxide being not greater than 80 angstroms and a thickness of said second gate oxide being not greater than 110 angstroms,
- and wherein said at least one voltage reducer comprises an N-transistor having a source connected to said external voltage source, a gate connected to said external voltage source and to ground via a voltage divider including a capacitor and a drain connected to at least some of said first plurality of transistors.
2 more elements
An integrated circuit arrangement comprising:
- transistors having predetermined upper voltage limits;
- the transistors are connected to each other and to an external voltage source having a single output voltage which is in excess of the predetermined upper voltage limits of a first plurality of said transistors, by a multi-layer metal structure;
- and at least one voltage reducer connected along said multi-layer metal structure between said external voltage source and said first plurality of said transistors,
- wherein said plurality of transistors each comprise a first gate oxide and said voltage reducer transistor comprises a second gate oxide and wherein said second gate oxide is thicker than the first gate oxide, a thickness of said first gate oxide being not greater than 80 angstroms and a thickness of said second gate oxide being not greater than 110 angstroms,
- and wherein said at least one voltage reducer comprises an N-transistor having a source connected to said external voltage source, a gate connected to said external voltage source and to ground via a voltage divider including a capacitor and a drain connected to at lease some of said first plurality of transistors.
2 more elements
An integrated circuit arrangement comprising:
- a multiplicity of transistors connected to each other and to an external voltage source having a voltage in excess of a predetermined voltage, by a multi-layer metal structure;
- and
- at least one voltage reducer connected along said multi-layer metal structure between said external voltage source and a first plurality of transistors forming part of said multiplicity of transistors, whereby the voltage supplied to said first plurality of transistors does not exceed said predetermined voltage,
- wherein said plurality of transistors each comprises a first gate oxide and said at least one voltage reducer transistor comprises a second gate oxide and wherein said second gate oxide is thicker than the first gate oxide, a thickness of said first gate oxide being not greater than 80 angstroms and a thickness of said second gate oxide being not greater than 110 angstroms,
- and wherein said at least one voltage reducer comprises an N-transistor having a source connected to said external voltage source, a gate connected to said external voltage source and to ground via a voltage divider including a capacitor and a drain connected to at least some of said first plurality of transistors.
2 more elements
Dependencies are inferred from the claim text.