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US 6,150,877 AGranted
Semiconductor device with improved circuit interconnection
AssigneeSharp Kabushiki Kaisha
InventorYoshinao Morikawa
Life of this patent
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Abstract
A semiconductor device includes a first circuit; a second circuit; and a plurality of data paths for transmitting a signal between the first circuit and the second circuit. Signal delay time periods when transmitting a signal through the plurality of data paths are substantially equal with each other.
Claims15
A semiconductor device, comprising:
- a plurality of first interconnects;
- a plurality of circuits;
- and
- a plurality of second interconnects for connecting the plurality of circuits to the first interconnects,
- wherein the plurality of second interconnects contains a plurality of groups of second interconnects, each of the plurality of groups of second interconnects being connected to the same first interconnect, and
- wherein a total length of each group of second interconnects is substantially equal to the total length of any other group of second interconnects.
3 more elements
A semiconductor device, comprising:
- a first circuit;
- a plurality of second circuits;
- and
- a plurality of data paths formed by a plurality of first interconnects and a plurality of groups of second interconnects connected between the first interconnects and the plurality of second circuits for transmitting a signal between the first circuit and the plurality of second circuits, wherein each of the plurality of groups of second interconnects are connected to the same first interconnect;
- and
- wherein the total length of each group of second interconnects is substantially equal to the total length of any other group of second interconnects so that signal delay time periods are substantially equal with each other when transmitting a signal through the plurality of data paths.
3 more elements
A semiconductor device, comprising:
- a plurality of first interconnects;
- and
- a plurality of groups of second interconnects connecting said plurality of first interconnects to a plurality of circuits, wherein each of said plurality of groups of second interconnects are connected to corresponding ones of said plurality of first interconnects, and wherein the total length of each of said plurality of groups of second interconnects are substantially equal to one another.
Dependencies are inferred from the claim text.