Method for the positioning/routing of a global clock circuit on an integrated circuit, and associated devices

A method for positioning/routing a global clock circuit on an integrated circuit, the method comprising the steps of:

• positioning a plurality of first conductive lines on the integrated circuit in a first direction, each first conductive line being connected to at least one first amplifier having an input receiving a clock signal;
• positioning functional blocks forming the integrated circuit and positioning a plurality of second conductive lines on the integrated circuit parallel to a second direction, each second conductive line connected to a functional block;
• positioning in each functional block at least one second amplifier having an adjustable input delay, and routing one of the plurality of second conductive lines to each second amplifier;
• determining an equivalent electrical diagram corresponding to a clock signal path originating from a source and an input of each second amplifier;
• simulating the equivalent electrical diagram and measuring a phase delay at the input of each second amplifier;
• and
• adjusting the input delay of each second amplifier to correspond to a largest measured phase delay.

An integrated circuit comprising:

• a plurality of functional blocks;
• a global clock circuit connected to said plurality of functional blocks providing a clock signal, said global clock circuit comprising
• a plurality of first amplifiers having an input receiving the clock signal, the clock signal originating from a source and forming a balanced tree-like structure with said plurality of first amplifiers,
• a plurality of first conductive lines parallel to a first direction, each first conductive line being connected to at least one of said plurality of first amplifiers, and
• a plurality of second conductive lines parallel to a second direction, each second conductive line being connected to at least one of said plurality of functional blocks;
• and
• each functional block comprising at least one second amplifier having an adjustable input delay connected to a closest one of said plurality of second conductive lines, the adjustable input delay being adjusted to correspond to a largest phase delay between the source clock signal and respective inputs of said plurality of second amplifiers.