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US 6,150,863 AGranted
User-controlled delay circuit for a programmable logic device
AssigneeXilinx, Inc.
InventorsRobert O. Conn, Peter H. Alfke
Life of this patent
Estimating the term…
Abstract
An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.
Claims15
An input block for an integrated circuit (IC), the input block comprising:
- a) an input terminal adapted to receive an input signal from a first source, the input signal including a first signal transition;
- b) a control terminal adapted to receive a delay instruction from a variable signal source, the delay instruction providing indicia of a delay period to apply to the first input signal, the variable signal source progressively changing the delay instruction such that the delay period progressively changes;
- c) a variable delay circuit having:
- an input node connected to the input terminal;
- an output node;
- at least one delay element for providing a delayed version of the input signal on the output node;
- and
- a control node adapted to receive the delay instruction from the control terminal,
- wherein the delayed version of the input signal includes a second signal transition delayed from the first signal transition by the delay period specified by the delay instruction;
- and
- d) a monitor element whereby the delayed version of the input signal on the output node is monitored for a metastable condition.
8 more elements
An input block for an integrated circuit (IC), the input block comprising:
- a) an input terminal adapted to receive an input signal from a first source, the input signal including a first signal transition;
- b) a control terminal adapted to receive a delay instruction from a variable signal source, the delay instruction providing indicia of a delay period to apply to the first input signal;
- and
- c) a variable delay circuit having:
- an input node connected to the input terminal;
- an output node;
- at least one delay element for providing a delayed version of the input signal on the output node, wherein the delayed version of the input signal includes a second signal transition delayed from the first signal transition by the delay period specified by the delay instruction;
- and
- a control node adapted to receive the delay instruction from the control terminal,
- wherein the variable signal source comprises a feedback circuit having at least one input terminal connected to the output node of the variable delay circuit and at least one output terminal providing control information to the control node of the variable delay circuit.
7 more elements
An input block for an integrated circuit (IC), the input block comprising:
- a) an input terminal adapted to receive an input signal from a first source, the input signal including a first signal transition;
- b) a control terminal adapted to receive a delay instruction from a variable signal source, the delay instruction providing indicia of a delay period to apply to the first input signal;
- c) a variable delay circuit having:
- an input node connected to the input terminal;
- an output node;
- at least one delay element for providing a delayed version of the input signal on the output node, wherein the delayed version of the input signal includes a second signal transition delayed from the first signal transition by the delay period specified by the delay instruction;
- and
- a control node adapted to receive the delay instruction from the control terminal;
- and
- d) a phase comparator having a first input terminal connected to the output node of the variable delay circuit, a second input terminal providing a reference clock signal, and an output terminal,
- wherein the variable signal source comprises a feedback circuit having an input terminal connected to the output terminal of the phase comparator and at least one output terminal providing control information to the control node of the variable delay circuit.
8 more elements
An integrated circuit, comprising:
- a first variable-delay circuit adapted to receive an input signal on an input terminal and to output a delayed version of the input signal on a first output terminal, the first variable delay circuit including at least one control terminal adapted to receive controls signals indicative of a delay duration to apply to the input signal;
- a control-signal generator having at least one output terminal connected to the at least one control terminal of the first variable-delay circuit, the control-signal generator being adapted to provide the control signals indicative of the delay duration, the control-signal generator progressively changing the control signals such that the delay duration progressively changes;
- and
- means for monitoring the delayed version of the input signal for a metastable condition.
1 more element
Dependencies are inferred from the claim text.