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US 6,150,862 AGranted
Stable delay buffer
AssigneeIntel Corporation
InventorOmer Vikinski
Life of this patent
Estimating the term…
Abstract
An apparatus that includes a driver circuit and an active load circuit coupled to an output of the driver circuit. The active load circuit is configured to actively adjust the slew rate of a signal outputted by the driver circuit.
Claims11
A circuit comprising:
- a driver circuit configured to output a signal;
- a load circuit coupled to the output of the driver circuit;
- and
- an active load circuit coupled to an output of the driver circuit, the active load circuit configured to actively adjust the slew rate of the signal wherein the active load circuit comprises:
- a capacitive load circuit;
- and
- a variable impedance circuit coupled between the driver circuit and the capacitive load circuit, the variable impedance circuit configured to adjust the slew rate in response to changes in fabrication process and operating conditions wherein the variable impedance circuit comprises:
- a first and a second nMOS transistor coupled between the output of the driver circuit and the capacitive load circuit;
- a first and a second pMOS transistor coupled between the output of the driver circuit and the capacitive load circuit, wherein a gate of the first nMOS transistor and a gate of the first pMOS transistor are coupled to an output of the load circuit;
- and
- an inverter having an input coupled to the output of the first load circuit, and an output coupled to a gate of the second nMOS transistor and to a gate of the second pMOS transistor.
8 more elements
A circuit comprising:
- a driver circuit configured to output a signal;
- a first load circuit coupled to an output of the driver circuit;
- and
- an active load circuit coupled the output of the driver circuit and an output from the first load circuit, the active load circuit being configured to actively adjust the slew rate of the signal in response to an output signal from the first load circuit wherein the active load circuit comprises:
- a capacitive load circuit;
- and
- a variable impedance circuit coupled between the driver circuit and the capacitive load circuit, the variable impedance circuit configured to adjust the slew rate in response to changes in fabrication process and operating conditions wherein the variable impedance circuit comprises:
- a first and a second nMOS transistor coupled between the output of the driver circuit and the capacitive load circuit;
- a first and a second pMOS transistor coupled between the output of the driver circuit and the capacitive load circuit, wherein a gate of the first nMOS transistor and a gate of the first pMOS transistor are coupled to an output of the first load circuit;
- and
- an inverter with an input coupled to the output of the first load circuit, wherein an inverted output of the inverter is coupled to a gate of the second nMOS transistor and to a gate of the second pMOS transistor.
8 more elements
Dependencies are inferred from the claim text.