Flip-flop

A shift register operable to receive an input signal and a clock signal and operable to generate an output signal, the shift register comprising:

• a plurality of flip-flops connected together in a sequence, at least one of the flip-flops having a latch circuit, a master flip-flop and a slave flip-flop, the latch circuit being operable to receive the clock signal and an output signal of a previous flip-flop in the sequence, and operable to generate an output signal tracking the input signal during a first portion of the clock signal, the output signal being constant during a second portion of the clock signal, the master flip-flop being operable to receive the clock signal and the output signal of the latch circuit, and operable to generate an output signal tracking the output signal of the latch circuit during the second portion of the clock signal, the output signal being constant during the first portion of the clock signal, the slave flip-flop being operable to receive the clock signal and the output signal of the master flip-flop, and operable to generate an output signal tracking the output signal of the master flip-flop during the first portion of the clock signal, the output signal being constant during the second portion of the clock signal;
• and
• a multiplexer operable to receive a data input signal, a mode determining signal and the output signal of the latch circuit, the multiplexer being operable to pass a selected one of the output signal of the latch circuit and that data input signal to the master flip-flop in response to the mode determining signal.

A shift register operable to receive an input signal and a clock signal and operable to generate an output signal, the shift register comprising:

• a first flip-flop operable to receive the input signal and the clock signal, and operable to generate an output signal in response to the input signal and the clock signal;
• a second flip-flop operable to receive the clock signal and the output signal of the first flip-flop, and operable to generate an output signal in response to the clock signal and the output signal of the first flip-flop, the second flip-flop having a latch circuit, a master flip-flop and a slave flip-flop, the latch circuit being operable to latch the output of the first flip-flop and generate an output signal tracking the input signal during a first portion of the clock signal, the output signal being constant during a second portion of the clock signal, the master flip-flop being operable to receive the clock signal and the output signal of the latch circuit, and operable to generate an output signal tracking the output signal of the latch circuit during the second portion of the clock signal, the output signal being constant during the first portion of the clock signal, the slave flip-flop being operable to receive the clock signal and the output signal of the master flip-flop, and operable to generate an output signal tracking the output signal of the master flip-flop during the first portion of the clock signal, the output signal being constant during the second portion of the clock signal;
• and
• a multiplexer operable to receive a data input signal, a mode determining signal and the output signal of the latch circuit, the multiplexer being operable to pass a selected one of the output signal of the latch circuit and that data input signal to the master flip-flop in response to the mode determining signal.