US 6,150,859 A · Digital delay-locked loop

Abstract

The present invention is directed to a digital delay-locked loop for digitally controlling a clock signal delay time and saving synchronization information in a register. After intercepting an input clock signal, the digital delay-locked loop utilizes the saved synchronization information in returning to the normal operation, and furthermore, detects a shifted delay by using a trigger pulse generator in order to reduce power consumption during the rapid synchronization of an internal clock signal to an external clock signal, saves a delay state corresponding to a maximum value of half the period of the external clock signal to a lock target rising edge of the internal clock signal, and thus synchronization time and operating time of the digital delay-loop are reduced, which results in reduced operation power for the predetermined time. In addition, even when the external clock signal is suspended, a lock point can be rapidly found and thereby mis-operation because internal clock signals in a circuit are not synchronized to the external clock signal can be minimized.

Claims19

Dependent claims

A digital delay-locked loop comprising:

a reference delay block that receives an internally generated delayed clock signal and generates a feedback clock signal;
a variable delay block including a delay chain having an unit delay line and a register chain to output the internally generated delayed clock signal in response to an externally inputted clock signal, wherein the variable delay block controls a delay time of the internally generated delayed clock signal;
a phase comparison block for comparing a phase difference between the feedback clock signal delayed by the reference delay block and the externally inputted clock signal;
and
a trigger pulse generator for generating a transfer pulse signal in accordance with a phase comparison control signal and a lock signal outputted from the phase comparison block and the externally inputted clock signal.

2 more elements

A digital delay-locked loop, comprising:

a phase detector that receives a delayed external clock signal, a feedback clock signal, a comparison signal and a control signal, compares a difference between the feedback clock signal and the delayed external clock signal, and generates a divided clock signal, a phase comparison control signal, a lock signal and first and second shift signals;
a trigger pulse generator coupled to the phase detector that receives the lock signal, the delayed external clock signal and the phase comparison control signal and generates a transfer pulse signal;
a variable delay block coupled to the phase detector and the trigger pulse generator that receives the first and second shift signals, the divided clock signal, the delayed external clock signal, and the transfer pulse signal and generates a delayed output clock signal and the comparison signal;
and
a reference delay block that receives the delayed output clock signal and generates the feedback clock signal.

2 more elements

Dependencies are inferred from the claim text.

Digital delay-locked loop

Life of this patent

Digital delay-locked loop

Life of this patent

Abstract

Claims19