Phase compensation circuit of digital processing PLL
AssigneeLG Information & Communications, Ltd.
InventorWon Sik Sung
Life of this patent
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Abstract
The present invention is to provide a phase compensation circuit of a DPPLL capable of hitless switching during switching the system clock, by exact matching frequency and phase of the DPPLL about phase difference which is less than minimum differential phase which may be detectable the way of digital and by distinguishing phase difference about the other party clock such that each clock unit commonly has the clock generated from the pair of clock units, alternatively and by switching the system clock in case that there is no difference after distinguishing, in the clock supplying system using the pair of lock units which have the phases that is asynchronized to the reference clock.
Claims11
A digital processing phase-locked loop (DPPLL), comprising:
- a first detecting path converting a value of a phase difference pulse outputted from a phase comparator into a digital first phase difference value,
- a second detecting path converting the value of the phase difference pulse into an analog value and producing a second phase difference value,
- control means for comparing the digital first phase difference value with a system clock value and selecting and outputting the second phase difference value in a case that the digital first phase difference value is smaller than a specific range of the system clock value, and
- voltage controlled oscillating means for outputting a phase compensated system clock by using the phase difference value outputted from the control means.
A digital processing phase-locked loop (DPPLL), comprising:
- a first detecting path converting a value of a phase difference pulse outputted from a phase comparator into a digital first phase difference value,
- a second detecting path converting the value of the phase difference pulse into an analog value and producing a second phase difference value,
- control means for comparing the digital first phase difference value with a system clock value and selecting and outputting the second phase difference value in a case that the digital first phase difference value is smaller than a specific range of the system clock value,
- voltage controlled oscillating means for outputting a phase compensated system clock by using the phase difference value outputted from the control means, and
- phase switching means for switching a system clock by comparing a phase of the phase compensated system clock with a phase of a second phase compensated system clock and detecting an area where a phase difference is smallest.
Dependencies are inferred from the claim text.