Integrated unit gain output stage
AssigneeSGS-Thomson Microelectronics S.A.
InventorsFrancesco Chrappan, Maurizio Nessi, Alberto Salina
Life of this patent
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Abstract
The operation of externally connected output power transistors of a class AB amplifier is controlled without employing any external sensing resistance of the output current by driving an externally connected power transistor through a level shifting buffer and employing a limiting network composed of an integrated transistor driven by the output of a signal amplifying stage and a resistance connected in series with its drain. The buffer stage shifts the level of the driving signal of the external power transistor by a value equal to the threshold voltage of the integrated transistor of the limiting network thus ensuring the turn-off of the external power transistor under quiescent conditions.
Claims22
An integrated circuit for driving at least one pair of discrete power field-effect transistors of a first majority-carrier conductivity type, said pair including a first transistor which has a source thereof connected to a first power supply voltage and a drain thereof connected to an output terminal, and said pair also including a second transistor which has a drain thereof connected to a second power supply voltage and a source thereof connected to said output terminal;
- said integrated circuit comprising:
- a connection for receiving an amplified analog input signal;
- a buffer connected to drive the gate of said second transistor and functionally connected to said amplified input signal;
- a diode-connected transistor of said first majority-carrier conductivity type, having a source terminal thereof connected to said output terminal, and having a drain terminal which is connected to be biased into conduction;
- a differential amplifier which is connected to receive, as differential inputs thereto, said amplified input voltage and the voltage of said drain of said diode-connected transistor, and which provides an output for driving the gate of said first transistor;
- and
- a limiting network comprising a field effect transistor which has a source terminal connected to said output terminal, and a drain terminal connected through a resistor to said second power supply voltage;
- wherein said limiting network provides a current contribution to avoid zero-crossing distortion to an output signal of the integrated circuit.
A method for controlling the operation of a pair of power transistors, said pair including a first transistor which has a source thereof connected to an output terminal and a drain connected to a power supply voltage, said method comprising:
- using a buffer stage to drive said first transistor, said buffer stage being functionally connected between the output node of an amplifying stage of a driving signal and the gate of said first transistor;
- using a limiting network comprising a field effect transistor to reproduce within the integrated control circuit said first transistor, said field effect transistor and a resistance being connected in series between said power supply and the output node;
- wherein said field effect transistor has a source terminal connected to said output terminal and a drain terminal connected through a resistor to said power supply voltage;
- and
- wherein said buffer has the function of shifting the level of an analog input signal by a value equal to the threshold voltage of the field effect transistor of the limiting network, under quiescent bias conditions;
- wherein said limiting network provides a current contribution to avoid zero-crossing distortion to an output signal of the integrated circuit.
A driving circuit for a class AB output stage comprising a pair of power transistors, at least one of said power transistors being external to a chip which includes said driving circuit, said driving circuit comprising:
- a differential amplifier for comparing the output voltage of a signal amplifying stage with a voltage present on the anode of a diode having a cathode connected to an output node of the output stage and directly biased by a current generator which supplies a quiescent current to the diode and the transistor of said pair that is controlled by the output of said differential amplifier;
- a buffer stage for driving said external power transistor, functionally connected between an output node of said signal amplifying stage and a control terminal of said external power transistor;
- a limiting network comprising at least a field effect transistor, which is driven by the output of said signal amplifying stage, and a resistance connected in series between a power supply node and said output node of the output stage;
- wherein said limiting network provides a current contribution to avoid zero-crossing distortion to an output signal of the integrated circuit.
A bridge amplifier comprising:
- two output stages each of which is composed of a pair of power transistors, said pair including a first transistor which has a source thereof connected to a first power supply voltage and a drain thereof connected to an output terminal, and said pair also including a second transistor which has a drain thereof connected to a second power supply voltage and a source thereof connected to said output terminal, at least one of said power transistors being external to a chip containing a respective integrated driving circuit, said integrated driving circuits each comprising:
- a connection for receiving an amplified analog input signal;
- a buffer connected to drive the gate of said second transistor and functionally connected to said amplified input signal;
- a diode-connected transistor of said first majority-carrier conductivity type, having a source terminal thereof connected to said output terminal, and having a drain terminal which is connected to be biased into conduction;
- a differential amplifier which is connected to receive, as differential inputs thereto, said amplified input voltage and the voltage of said drain of said diode-connected transistor, and which provides an output for driving the gate of said first transistor;
- and
- a limiting network comprising a field effect transistor which has a source terminal connected to said output terminal, and a drain terminal connected through a resistor to said second power supply voltage;
- wherein said limiting network provides a current contribution to avoid zero-crossing distortion to an output signal of the integrated circuit.
An integrated circuit, for driving at least one pair of discrete power field-effect transistors of a first majority-carrier conductivity type, said pair including a first transistor which has a source thereof connected to a first power supply voltage and a drain thereof connected to an output terminal, and said pair also including a second transistor which has a drain thereof connected to a second power supply voltage and a source thereof connected to said output terminal;
- said integrated circuit comprising:
- a connection for receiving an amplified analog input signal which is functionally connected to the gate of said second power transistor;
- a diode-connected transistor of said first majority-carrier conductivity type, having a source terminal thereof connected to said output terminal, and having a drain terminal which is connected to be biased into conduction;
- a differential amplifier which is connected to receive, as differential inputs thereto, said amplified input voltage and the voltage of said drain of said diode-connected transistor, and which provides an output for driving the gate of said first transistor;
- and
- a limiting network comprising a field effect transistor which has a source terminal connected to said output terminal, and a drain terminal connected through a resistor to said second power supply voltage;
- wherein said limiting network provides a current contribution to avoid zero-crossing distortion to an output signal of the integrated circuit.
Dependencies are inferred from the claim text.