US 6,150,851 A · Charge transfer amplifier circuit, voltage comparator, and sense amplifier

Abstract

Charge transfer amplifier circuit which is capable of canceling fluctuations in the element characteristics thereof and which conducts highly accurate voltage amplification without the use of a stationary current, and provides a voltage comparator which may be applied to a highly accurate A/D converter which has low power consumption. The charge transfer amplifier circuit is provided with a MOS transistor, a first capacity and a second capacity which are effectively connected to, respectively, the source electrode and the drain electrode of the MOS transistor, a mechanism for setting the region between the terminals of the first capacity and the region between the terminals of the second capacity, respectively, to appropriate predetermined potential differences, and for releasing these, and a mechanism for appropriately externally altering the potential difference between the gate and the source of the MOS transistor. The first capacity is set so as to be larger than the second capacity. Furthermore, in the voltage comparator, a dynamic latch circuit is connected to the drain electrode of the charge transfer amplifier circuit.

Claims16

Dependent claims

A charge transfer amplifier circuit, comprising:

a MOS transistor having a gate, source and drain electrode;
a first capacitor and a second capacitor which are respectively connected with said source electrode and drain electrode of said MOS transistor;
means for setting the region between the terminals of said first capacitor and the region between the terminals of said second capacitor to a respective predetermined potential difference, and for releasing the respective predetermined potential difference of said first capacitor and said second capacitor;
and
means for externally altering the potential difference between said gate and source electrodes of said MOS transistor, said first capacitor set so as to be larger than said second capacitor.

2 more elements

A charge transfer amplifier circuit comprising:

a first circuit, having a PMOS transistor with a gate, source and drain electrode, a first capacitor having terminals, said first capacitor which is connected with said source electrode of the PMOS transistor, a first means for setting the region between the terminals of said first capacitor to a predetermined potential difference, and for releasing said predetermined potential difference set by said first means, and a means for appropriately externally altering the potential difference between the gate electrode and the source electrode of said PMOS transistor, and
a second circuit, having a NMOS transistor with a gate, source and drain electrode, a second capacitor having terminals which is effectively connected to the source electrode of said NMOS transistor, a second means for setting the region between the terminals of said second capacitor to an appropriate predetermined potential difference and for releasing said predetermined potential difference set by said second means, and a means for appropriately externally altering the potential difference between the gate electrode and the source electrode of said NMOS transistor;
said first circuit and said second circuit are connected at the drain electrodes of said PMOS transistor and said NMOS transistor, a third means is provided for setting the region between the terminals of a third capacitor, which is effectively connected to these drain electrodes, to an appropriate predetermined potential difference, and for releasing said predetermined potential difference set by said third means, wherein each of said first capacitor of said first circuit and said second capacitor of said second circuit being larger than said third capacitor.

A charge transfer positive feedback amplifier circuit, which is provided with:

a first MOS transistor;
a second MOS transistor, which is of the opposite conductivity type to said first MOS transistor;
a storage capacity, which is connected between the source electrode of said first MOS transistor and the source electrode of said second MOS transistor;
a means for setting both terminals of said storage capacity to an appropriate predetermined potential in a reset period;
a means for connecting the gate electrode of said second MOS transistor and the drain electrode of said first MOS transistor, a means for setting the drain electrode of said first MOS transistor to an appropriate predetermined potential in a precharge period which follows the reset period, and for releasing this in an amplification period following said precharge period;
a means for connecting the gate electrode of said first MOS transistor and the drain electrode of said second MOS transistor, and a means for setting the drain electrode of said second MOS transistor to an appropriate predetermined potential in said precharge period and releasing this in said amplification period;
and
a mechanism for altering one of the gate/source voltage of said first MOS transistor and the gate/source voltage of said second MOS transistor in response to an input signal, the voltage of which changes, in said amplification period.

5 more elements

A voltage comparator, comprising:

an input circuit having an output end;
a charge transfer amplifier circuit having an input end and an output end, the input end of said amplifier circuit being operatively coupled to the output end of said input circuit;
and
a dynamic latch circuit having an input end and an output end, the input end of said dynamic latch circuit being operatively coupled to the output end of said charge transfer amplifier circuit;
said charge transfer amplifier circuit comprising:
a first circuit having a PMOS transistor with a gate, source and drain electrode, the gate electrode of said PMOS transistor being operatively coupled at the input end of said amplifier circuit to the output end of said input circuit, the drain electrode of said PMOS transistor being operatively coupled at the output end of said amplifier circuit to the input end of said dynamic latch circuit,
said first circuit further including a first capacitor having terminals, said first capacitor being connected with the source electrode of said PMOS transistor, and a first means for setting the region between the terminals of said first capacitor to a predetermined potential difference and for releasing the predetermined potential difference set by said first means, and
a second circuit having a NMOS transistor with a gate, source and drain electrode, the gate electrode of said NMOS transistor being operatively coupled at the input end of said amplifier circuit to the output end of said input circuit, the drain electrode of said NMOS transistor being operatively coupled at the output end of said amplifier circuit to the input end of said dynamic latch circuit,
said second circuit further including a second capacitor having terminals, said second capacitor being connected with the source electrode of said NMOS transistor, and a second means for setting the region between the terminals of said second capacitor to a predetermined potential difference and for releasing the predetermined potential difference set by said second means,
said first circuit and said second circuit being connected at the respective drain electrodes of said PMOS transistor and said NMOS transistor;
said input circuit including a means, operatively associated with said first circuit and said second circuit, for appropriately selectably altering the potential difference between the gate electrode and the source electrode of said PMOS transistor and for appropriately selectably altering the potential difference between the gate electrode and the source electrode of said NMOS transistor.

8 more elements

A voltage comparator, comprising:

an input circuit having an output end;
a charge transfer amplifier circuit having an input end and an output end, the input end of said amplifier circuit being operatively coupled to the output end of said input circuit;
and
a dynamic latch circuit having an input end and an output end, the input end of said dynamic latch circuit being operatively coupled to the output end of said charge transfer amplifier circuit;
said charge transfer amplifier circuit comprising:
a first circuit having a PMOS transistor with a gate, source and drain electrode, the gate electrode of said PMOS transistor being operatively coupled at the input end of said amplifier circuit to the output end of said input circuit, the drain electrode of said PMOS transistor being operatively coupled at the output end of said amplifier circuit to the input end of said dynamic latch circuit,
said first circuit further including a first capacitor having terminals, said first capacitor being connected with the source electrode of said PMOS transistor, and a first means for setting the region between the terminals of said first capacitor to a predetermined potential difference and for releasing the predetermined potential difference set by said first means, and
a second circuit having a NMOS transistor with a gate, source and drain electrode, the gate electrode of said NMOS transistor being operatively coupled at the input end of said amplifier circuit to the output end of said input circuit, the drain electrode of said NMOS transistor being operatively coupled at the output end of said amplifier circuit to the input end of said dynamic latch circuit,
said second circuit further including a second capacitor having terminals, said second capacitor being connected with the source electrode of said NMOS transistor, and a second means for setting the region between the terminals of said second capacitor to a predetermined potential difference and for releasing the predetermined potential difference set by said second means,
said first circuit and said second circuit being connected at the respective drain electrodes of said PMOS transistor and said NMOS transistor, the gate electrode of said PMOS transistor and the gate electrode of said NMOS transistor being connected together to form a common terminal;
said input circuit including a means, operatively associated with said first circuit and said second circuit, for appropriately selectably altering the potential difference between the gate electrode and the source electrode of said PMOS transistor and for appropriately selectably altering the potential difference between the gate electrode and the source electrode of said NMOS transistor.

8 more elements

A voltage comparator, comprising:

an input circuit having an output end;
a charge transfer positive feedback amplifier circuit having at least a first circuit junction and a second circuit junction, one of the first circuit junction and the second circuit junction serving as an input for said amplifier circuit while another of the first circuit junction and the second circuit junction serving as an output for said amplifier circuit;
a dynamic latch circuit having an input end and an output end;
one of the first circuit junction and the second circuit junction being operatively coupled to the output end of said input circuit while another of the first circuit junction and the second circuit junction being operatively coupled to the input end of said dynamic latch circuit;
said charge transfer positive feedback amplifier circuit comprising:
a first MOS transistor,
a second MOS transistor, which is of the opposite conductivity type to said first MOS transistor,
a storage capacity, which is connected between the source electrode of said first MOS transistor and the source electrode of said second MOS transistor,
a means for setting both terminals of said storage capacity to an appropriate predetermined potential in a reset period,
a means for connecting the gate electrode of said second MOS transistor and the drain electrode of said first MOS transistor,
a means for connecting the gate electrode of said first MOS transistor and the drain electrode of said second MOS transistor,
a first means, operatively coupled to one of the first circuit junction and the second circuit junction, for setting the drain electrode of said first MOS transistor to an appropriate predetermined potential in a precharge period which follows the reset period, and for releasing the predetermined potential set by said first means in an amplification period following said precharge period, and
a second means, operatively coupled to another of the first circuit junction and the second circuit junction, for setting the drain electrode of said second MOS transistor to an appropriate predetermined potential in said precharge period, and for releasing the predetermined potential set by said second means in said amplification period;
said input circuit including a mechanism for selectably altering one of the gate/source voltage of said first MOS transistor and the gate/source voltage of said second MOS transistor in response to an input signal, the voltage of which changes, in said amplification period.

11 more elements

A voltage comparator, comprising:

an input circuit having an output end;
a circuit assembly having at least a first circuit junction and a second circuit junction, one of the first circuit junction and the second circuit junction serving as an input for said circuit assembly while another of the first circuit junction and the second circuit junction serving as an output for said circuit assembly, said circuit assembly including a first charge transfer positive feedback amplifier circuit and a second charge transfer positive feedback amplifier circuit;
a dynamic latch circuit having an input end and an output end;
one of the first circuit junction and the second circuit junction being operatively coupled to the output end of said input circuit while another of the first circuit junction and the second circuit junction being operatively coupled to the input end of said dynamic latch circuit;
each respective one of said first charge transfer positive feedback amplifier circuit and said second charge transfer positive feedback amplifier circuit respectively comprising:
a first MOS transistor,
a second MOS transistor, which is of the opposite conductivity type to said first MOS transistor,
a storage capacity, which is connected between the source electrode of said first MOS transistor and the source electrode of said second MOS transistor,
a means for setting both terminals of said storage capacity to an appropriate predetermined potential in a reset period,
a means for connecting the gate electrode of said second MOS transistor and the drain electrode of said first MOS transistor, and
a means for connecting the gate electrode of said first MOS transistor and the drain electrode of said second MOS transistor;
the first MOS transistor of said first charge transfer positive feedback amplifier circuit including a P-type MOS transistor, and the first MOS transistor of said second charge transfer positive feedback amplifier circuit including an N-type MOS transistor;
wherein the drain electrode of the P-type MOS transistor of said first charge transfer positive feedback amplifier circuit and the drain electrode of the N-type MOS transistor of said second charge transfer positive feedback amplifier circuit are connected at one of the first circuit junction and the second circuit junction, and the drain electrode of the N-type MOS transistor of said first charge transfer positive feedback amplifier circuit and the drain electrode of the P-type MOS transistor of said second charge transfer positive feedback amplifier circuit are connected at another of the first circuit junction and the second circuit junction;
a first means, operatively coupled to one of the first circuit junction and the second circuit junction, for setting the respective drain electrodes of the respective first MOS transistors of said first charge transfer positive feedback amplifier circuit and said second charge transfer positive feedback amplifier circuit to an appropriate predetermined potential in a precharge period which follows the reset period, and for releasing the predetermined potential set by said first means in an amplification period following said precharge period;
and
a second means, operatively coupled to another of the first circuit junction and the second circuit junction, for setting the respective drain electrodes of the respective second MOS transistors of said first charge transfer positive feedback amplifier circuit and said second charge transfer positive feedback amplifier circuit to an appropriate predetermined potential in said precharge period, and for releasing the predetermined potential set by said second means in said amplification period;
said input circuit including a mechanism for selectably altering one of the respective gate/source voltages of the respective first MOS transistors of said first charge transfer positive feedback amplifier circuit and said second charge transfer positive feedback amplifier circuit and the respective gate/source voltages of the respective second MOS transistors of said first charge transfer positive feedback amplifier circuit and said second charge transfer positive feedback amplifier circuit, in response to an input signal, the voltage of which changes, in said amplification period.

14 more elements

An amplifier assembly, comprising:

a circuit assembly including a first charge transfer positive feedback amplifier circuit and a second charge transfer positive feedback amplifier circuit;
each respective one of said first charge transfer positive feedback amplifier circuit and said second charge transfer positive feedback amplifier circuit respectively comprising:
a first MOS transistor,
a second MOS transistor, which is of the opposite conductivity type to said first MOS transistor,
a storage capacity, which is connected between the source electrode of said first MOS transistor and the source electrode of said second MOS transistor,
a means for setting both terminals of said storage capacity to an appropriate predetermined potential in a reset period,
a means for connecting the gate electrode of said second MOS transistor and the drain electrode of said first MOS transistor, and a first means for setting the drain electrode of said first MOS transistor to an appropriate predetermined potential in a precharge period which follows the reset period, and for releasing the predetermined potential set by said first means in an amplification period following said precharge period, and
a means for connecting the gate electrode of said first MOS transistor and the drain electrode of said second MOS transistor, and a second means for setting the drain electrode of said second MOS transistor to an appropriate predetermined potential in said precharge period, and for releasing the predetermined potential set by said second means in said amplification period;
the first MOS transistor of said first charge transfer positive feedback amplifier circuit including a P-type MOS transistor, and the first MOS transistor of said second charge transfer positive feedback amplifier circuit including an N-type MOS transistor;
wherein the drain electrode of the P-type MOS transistor of said first charge transfer positive feedback amplifier circuit and the drain electrode of the N-type MOS transistor of said second charge transfer positive feedback amplifier circuit are connected, and the drain electrode of the N-type MOS transistor of said first charge transfer positive feedback amplifier circuit and the drain electrode of the P-type MOS transistor of said second charge transfer positive feedback amplifier circuit are connected;
and
a mechanism for selectably altering one of the respective gate/source voltages of the respective first MOS transistors of said first charge transfer positive feedback amplifier circuit and said second charge transfer positive feedback amplifier circuit and the respective gate/source voltages of the respective second MOS transistors of said first charge transfer positive feedback amplifier circuit and said second charge transfer positive feedback amplifier circuit, in response to an input signal, the voltage of which changes, in said amplification period;
said mechanism comprising at least one selectively accessible data memory element.

10 more elements

Dependencies are inferred from the claim text.

Charge transfer amplifier circuit, voltage comparator, and sense amplifier

Life of this patent

Charge transfer amplifier circuit, voltage comparator, and sense amplifier

Life of this patent

Abstract

Claims16