Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication

Abstract

A two-phase dynamic logic circuit for complementary GaAs HIGFET fabrication processes has a precharge transistor connected between a precharge volt source and an output node of the logic circuit. The precharge transistor is controlled by a clock signal such that the output node precharges when the clock signal is low and is isolated from the precharge voltage source when the clock signal is high. An evaluate transistor connected to the output node and an NFET logic block has a first terminal connected to the evaluate transistor such that the evaluate transistor is between the NFET logic block and the output node. A second terminal of the logic block is connected to a voltage source and a data input terminal that is arranged to receive data input signals. The NFET logic block includes on or more transistor(s) is arranged to generate a logic value. The evaluate transistor is controlled by the clock signal such that when the clock signal is low, the output node is isolated form the NFET logic block, and when the clock signal is high, the logic value generated by the logic block is allowed to determine the voltage on the output node of the logic circuit. A pass-gate is arranged to receive an input signal and conditionally pass the input signal to the gate(s) of the transistor(s) in the NFET logic block under the control of the clock signal such that the input is allowed to influence the gate voltage of the evaluation transistor when the clock signal is low, but is not allowed to influence the gate voltage of the transistor(s) in the logic block when the clock signal is high.

Dependencies are inferred from the claim text.