Bus hold circuit with overvoltage tolerance

An undervoltage tolerant bus-hold circuit designed to operate in three states including a high-impedance state, an input node, and an output node, wherein the bus-hold circuit is a CMOS-based circuit couplable between a high-potential power rail and a low-potential power rail, the circuit comprising:

• a. an input inverter having an input coupled to the input node and an output coupled to the output node, wherein said input inverter is powered by the high-potential power rail;
• b. a latching inverter having an input coupled to the output node and an output coupled to the input node;
• c. a sense circuit coupled to the input node and to the low-potential power rail;
• and
• d. an arbiter circuit coupled to said sense circuit and to the input node,
• wherein said sense circuit and said arbiter circuit selectively establish in combination a pseudo low-potential power rail having a potential that is the lower of either the potential associated with the input node or the potential associated with the low-potential power rail, wherein said pseudo low-potential power rail is coupled to said latching inverter.

A bus-hold circuit designed in three states including a high-impedance state, wherein the bus-hold circuit is a CMOS-based circuit including an input node and an output node, and is couplable between a high-potential power rail and a low-potential power rail, the circuit comprising:

• a. a latching inverter having an input coupled to the output node and an output coupled to the input node;
• b. a sense circuit coupled to the input node;
• and
• c. an arbiter circuit coupled to said sense circuit and to the input node,
• wherein said sense circuit and said arbiter circuit selectively establish in combination a pseudo power rail to power said latching inverter, wherein any potential at the input node in excess of the potential of either the high-potential power rail or the low-potential power rail is the potential of said pseudo power rail.

A process to control a bus-hold circuit capable of operating in three states including a high-impedance state, wherein the bus-hold circuit is a CMOS-based circuit including an input node and an output node, and is couplable between a high-potential power rail and a low-potential power rail, the process comprising the steps of:

• a. providing a latching inverter between the input node and the output node;
• b. sensing a potential associated with the input node and with the high potential power rail and the low potential power rail;
• and
• c. selecting a potential in excess of the potential of either of the high-potential power rail and the low-potential power rail to establish a pseudo power rail to power said latching inverter.

A computer system including one or more circuit buses, wherein one or more of the one or more circuit buses includes coupled thereto a bus-hold circuit designed to operate in three states including a high-impedance state, wherein the bus-hold circuit is a CMOS-based circuit including an input node and an output node, and is couplable between a high-potential power rail and a low-potential power rail, the bus-hold circuit comprising:

• a. a latching inverter having an input coupled to the output node and an output coupled to the input node;
• b. a sense circuit coupled to the input node;
• and
• c. an arbiter circuit coupled to said sense circuit and to the input node,
• wherein said sense circuit and said arbiter circuit selectively establish in combination a pseudo power rail to power said latching inverter, wherein any potential at the input node in excess of the potential of either the high-potential power rail or the low-potential power rail is the potential of said pseudo power rail.