Five volt tolerant I/O buffer

A tri-state CMOS I/O buffer circuit having overvoltage protection, comprising:

• a PMOS driver transistor coupled to a supply voltage and to an I/O pad;
• a transmission gate including an NMOS transistor and a PMOS transistor connected in parallel, coupled to a gate electrode of the driver transistor, for passing voltages representing both high and low logic levels through the transmission gate in a first direction to the gate electrode of the driver transistor, and for blocking an overvoltage level from passing from the gate electrode of the driver transistor in a second direction opposite the first direction;
• control logic coupled to a gate electrode of the PMOS transistor, comprising first logic for controlling a conductive state of the PMOS transistor during an output enabled condition, and second logic for controlling a conductive state of the PMOS transistor during an output disabled condition, wherein each of the first control logic and the second control logic comprises multiple series-connected NMOS transistors;
• and
• a first PMOS protection transistor coupled between the pad and the gate electrode of the driver transistor for, when a pad voltage level exceeds the supply voltage, applying the pad voltage to the gate electrode of the driver transistor.