Variable grain architecture for FPGA integrated circuits

Abstract

A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2.times.L, 4.times.L, 8.times.L and direct connect surround each super-VGB to provide different kinds of interconnect.

Dependencies are inferred from the claim text.