US 6,150,841 AGranted

Enhanced macrocell module for high density CPLD architectures

AssigneeLattice Semiconductor Corporation

InventorsOm P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Chong M. Lee, Robert M. Balzli, Jr., Larry R. Metzger, Kerry A. Ilgenstein

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

An improved CPLD includes a plurality of macrocell modules (MM's) where each MM can receive a relatively large number of independent inputs (at least 80) and can generate at least 5 different product term signals (PT's) therefrom. All 5 PT's may be used for generating a local sum-of-products (SoP). Any of the 5 PT's may be stolen (steered-away) to instead provide a local control for its macrocell module. Each module includes a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules. Simple allocation and super-allocation may be used to produce sums-of-sums signals of relatively large, one-pass function depth, such as 160PT's in one pass.

Claims19

Dependent claims

A monolithic, Complex Programmable Logic Device (CPLD) for programmably implementing designs having parallel data words that are at least B bits wide, where B is an integer equal to or greater than 32, said CPLD having a plurality of more than B I/O terminals for communicating with external circuitry, said CPLD further comprising:

a plurality of macrocell modules operatively coupled to at least a subset of said I/O terminals, wherein each macrocell module includes:
(a) at least first through fifth product term generators for producing respective and local first through fifth product term signals, where each product term signal can represent at least up to B times 112.5%, independent input terms or more;
(b) a local SoP-producing gate, operatively coupled to receive a selected subset or all of the local product term signals and to produce therefrom a local SoP signal representing a Boolean sum-of-products of one or more of the respective and local product term signals (PT0-PT4);
(c) at least first through fifth PT steerers respectively coupled each to an output of a respective one of the first through fifth product term generators, wherein each PT steerer may be programmably configured to either direct to the local SoP-producing gate or steer-away the respective one of the local product term signals (PT0-PT4);
(d) a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules;
(e) a post-SoP steerer that can be programmably configured to direct to the local SoS-producing gate or steer-away to SoS-producing gates of neighboring macrocell modules, the local SoP signal;
and
(f) a local storage or storage plus combinatorial-pass-through element having an IN terminal, internal storage operatively coupled for receiving and storing a signal applied to the IN terminal, and a Q output terminal operatively coupled for outputting a signal stored in said storage, where said IN terminal of said local storage/pass-through element is operatively coupled to receive IN signals from one or more of said local SoS-producing gate and said PT steerers.

5 more elements

A method for implementing with a High Density Complex Programmable Logic Device (HCPLD), designs that are either 16-bits wide or 32-bits wide or 64-bits wide,

where said HCPLD is a monolithic device having at least 64 I/O terminals for communicating with external circuitry and at least 256 result-storing macrocell modules, and the macrocell modules of said CPLD further each comprises:
(0.1) at least first through fifth product term generators for producing respective and local product term signals each capable of representing up to B times 125%, independent input terms or more;
(0.2) a local SoP-producing gate that can produce a Boolean sum-of-products of one or more of the respective and local product term signals;
(0.3) at least first through fifth PT steerers respectively coupled each to an output of a respective one of the product term generators, wherein each PT steerer can be programmably configured to either direct to the local SoP-producing gate or steer-away the respective one of the local product term signals;
(0.4) a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules;
(0.5) a post-SoP steerer that can be programmably configured to direct to the local SoS-producing gate or steer-away to SoS-producing gates of neighboring macrocell modules, the local SoP signal;
and
(0.6) a local storage or local storage plus combinatorial-pass-through element having an IN terminal, internal storage, and a Q output terminal, where said IN terminal is operatively coupled to receive IN signals from one or more of said local SoS-producing gate and said PT steerers,
said method comprising two or more appropriate ones of the steps of:
(a) using one or more of said at least first through fifth PT steerers to steer-away the respective ones of the local product term signals each to a corresponding local control terminal of the macrocell module;
(b) using the local SoS-producing gate to produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules;
and
(c) using the post-SoP steerer to steer-away to SoS-producing gates of neighboring macrocell modules, the local SoP signal.

10 more elements

A monolithic, Complex Programmable Logic Device (CPLD) for programmably implementing designs which use parallel data words of at least a plurality of B bits each, said CPLD having a plurality of more than B I/O terminals for communicating with external circuitry, and said CPLD further comprising:

a plurality of macrocell modules operatively coupled to at least a subset of said I/O terminals, wherein each macrocell module includes:
(a) a local storage/pass-through element having an IN terminal, internal storage operatively coupled to the IN terminal for receiving and storing a signal applied to the IN terminal, and a Q output terminal that is programmably couplable to one or the other of the IN terminal and the internal storage, said Q output terminal outputting a corresponding macrocell output signal;
(b) at least first through fifth, local product term generators for producing respective and local product term signals of the macrocell module, where each local product term signal can represent a Boolean product of up to a first maximum number of independent input terms of the macrocell module, said first maximum number being greater than B;
(c) a local SoP-producing gate, operatively coupled to receive a selected subset or all of the local product term signals of the local macrocell module and to produce therefrom a local SoP signal representing a Boolean sum-of-products of one or more of the respective and local product term signals;
(d) at least first through fifth PT steerers respectively coupled each to an output of a respective one of the product term generators of the macrocell module, wherein each PT steerer may be programmably configured to either direct to the local SoP-producing gate or steer-away the respective one of the local product term signals,
(c.1) wherein, if so steered away, each steered-away one of the local product term signals can be used for defining a locally-selectable function of the corresponding macrocell module;
(d) a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules;
(e) a post-SoP steerer that can be programmably configured to direct to the local SoS-producing gate or steer-away to SoS-producing gates of neighboring macrocell modules, the local SoP signal;
and
(f) a post-SoS steerer, operatively coupled to the IN terminal of the local storage/pass-through element and programmably configurable to direct toward said IN terminal or steer-away to SoS-producing gates of neighboring macrocell modules, the local SoS signal.

7 more elements

Dependencies are inferred from the claim text.