Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM

A field programmable gate array (FPGA) comprising:

• a first configurable logic block having a corresponding first set of configuration memory cells;
• a first configuration cache memory array coupled to the first configurable logic block, wherein the first configuration cache memory array stores values to be loaded into the first set of configurable memory cells, thereby reconfiguring the first configurable logic block;
• a second configuration cache memory array coupled to the first configuration cache memory array, wherein the second configuration cache memory array stores values to be loaded into the first set of configurable memory cells, thereby reconfiguring the first configurable logic block;
• and
• control circuitry for transferring values from the second configuration cache memory array to the first configuration cache memory array.

A field programmable gate array (FPGA) comprising:

• a configurable logic block having a corresponding set of configuration memory cells;
• a random access memory (RAM) block coupled to the configurable logic block, the RAM block having a plurality of local cache memories;
• first control circuitry for transferring values stored in one of the local cache memories to the set of configuration memory cells, thereby reconfiguring the configurable logic block;
• and
• second control circuitry for accessing any number of the local cache memories as random access memory through the configurable logic block.