Elimination of SOI parasitic bipolar effect
AssigneeInternational Business Machines Corporation
InventorsMichael Kevin Ciraula, Christopher McCall Durham, Peter Juergen Klim
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Abstract
The present invention addresses the foregoing needs by providing a circuit implemented in SOI (silicon on insulator) CMOS, which includes a first node precharged to an activated level, a first transistor coupled between the first node and the second node, a second transistor coupled between the second node and a ground potential, and a third transistor coupled to the second node and operable for preventing the second node from rising to the activated level. The third transistor prevents the parasitic bipolar effect from raising this second node to the activated level. Essentially, the third transistor maintains the second node substantially at a ground level.
Claims18
A circuit implemented in SOI CMOS comprising:
- a first node precharged to an activated level;
- a first transistor coupled between the first node and a second node, wherein the first transistor is off;
- a second transistor coupled between the second node and a ground potential;
- and
- a third transistor coupled to the second node for preventing the second node from rising to the activated level, wherein the third transistor prevents a parasitic bipolar effect from raising the second node to the activated level.
A circuit implemented in SOI CMOS comprising:
- a first node precharged to an activated level;
- a first transistor coupled between the first node and a second node;
- a second transistor coupled between the second node and a ground potential;
- and
- a third transistor coupled to the second node for preventing the second node from rising to the activated level, wherein the third transistor maintains the second node substantially at a ground level.
A method comprising the steps of:
- coupling a precharged node to a first SOI CMOS transistor;
- coupling the first SOI CMOS transistor to a second node;
- coupling the second node to a ground potential through a third SOI CMOS transistor;
- and
- preventing the second node from rising to a level of the precharged node, wherein the preventing step includes the step of coupling a third transistor to the second node, wherein the third transistor prevents a parasitic bipolar effect from raising the second node to the level of the precharged node.
A multiplexor ("mux") implemented in SOI CMOS comprising:
- a first node precharged to an activated level;
- a first transistor coupled between the first node and a second node, wherein the first transistor is off;
- a second transistor coupled between the second node and a ground potential;
- and
- a third transistor coupled to the second node for preventing the second node from rising to the activated level, wherein the third transistor prevents a parasitic bipolar effect from raising the second node to the activated level.
A circuit implemented in SOI CMOS comprising:
- a first node precharged to an activated level;
- a first transistor coupled between the first node and a second node;
- a second transistor coupled between the second node and a ground potential;
- and
- a third transistor coupled to the second node for preventing the second node from rising to the activated level, wherein the third transistor prevents a parasitic bipolar effect from raising the second node to the activated level.
A method comprising the steps of:
- coupling a precharged node to a first SOI CMOS transistor;
- coupling the first-SOI CMOS transistor to a second node;
- coupling the second node to a ground potential to a third SO CMOS transistor;
- and
- preventing the second node from rising to a level of the precharged node, wherein the third transistor prevents a parasitic bipolar effect from raising the second node to the level of the precharged node.
A multiplexor ("mux") implemented in SOI CMOS comprising:
- a first node precharged to an activated level;
- a first transistor coupled between the first node and a second node;
- a second transistor coupled between the second node and a ground potential;
- and
- a third transistor coupled to the second node for preventing the second node from rising to the activated level, wherein the third transistor prevents a parasitic bipolar effect from raising the second note to the activated level.
Dependencies are inferred from the claim text.