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US 6,150,807 AGranted
Integrated circuit architecture having an array of test cells providing full controllability for automatic circuit verification
AssigneeLightspeed Semiconductor Corporation
InventorRobert Osann, Jr.
Life of this patent
Estimating the term…
Abstract
A new circuit architecture is provided for testing digital integrated circuits which allows one to arbitrarily force any combination of logic values to be simultaneously driven onto any combination of internal nets. This allows all of the connections to each internal logic cell, and the logic cell itself, to be verified by applying a set of test patterns to each logic cell individually. In this way, the integrity of the entire device can be verified without having knowledge of the operation of the circuit as a whole.
Claims3
An integrated circuit, comprising:
- a prefabricated array of logic cells, couplable to form an arbitrary circuit, wherein a plurality of logic cells in said array each includes a cell output;
- and wherein each logic cell in said plurality of logic cells is capable, in its prefabricated state, of selectively producing, independent of said other logic cells and at said logic cell's respective cell output, a test value, which test value is independent of said arbitrary circuit, and a logic value, which logic value will be determined by said arbitrary circuit.
A method of forming an integrated circuit, comprising:
- forming a prefabricated array of logic cells, couplable to form an arbitrary circuit, and prefabricated array independent of said arbitrary circuit, wherein each logic cell has a cell output, and wherein each logic cell is capable, in its prefabricated state, of selectively producing, independent of other logic cells in said prefabricated array and at said logic cell's respective cell output, a test value, which test value is independent of said arbitrary circuit, and a logic value, which logic value will be determined by said arbitrary circuit;
- and
- forming said arbitrary circuit specified by a user by coupling some of said logic cells in said array of logic cells to other logic cells in said array of logic cells.
Dependencies are inferred from the claim text.