Chip-scale semiconductor package
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsChih-Ming Chung, Kuo-Pin Yang, Jen-Kuang Fang, Su Tao
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AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsChih-Ming Chung, Kuo-Pin Yang, Jen-Kuang Fang, Su Tao
Estimating the term…
A chip-scale semiconductor package mainly includes a semiconductor chip, a substrate and a package body. Said chip is attached onto said substrate by an adhesive layer. Said chip has a plurality of bonding pads formed thereon. Said adhesive layer has an aperture corresponding to the bonding pads of said chip such that the bonding pads can be exposed within an aperture. Said substrate has several through-holes respectively corresponding to the bonding pads of said chip and parts of the area around the edge of said chip for dispensing of encapsulant after the soldering of leads of said substrate to the bonding pads of said chip. The encapsulant dispensed into the through-holes can flow from the surface of said chip to the edge thereof. Said package body has one portion provided within the through-hole of said substrate and another portion provided around the edge of said chip whereby encapsulation process is accomplished without having to turn the whole semiconductor package device.
A chip scale semiconductor package comprising:
Dependencies are inferred from the claim text.