Ldmos transistor with thick copper interconnect

An LDMOS transistor comprising:

• a semiconductor substrate;
• a plurality of striped diffusions of a first conductivity type disposed within said semiconductor substrate;
• a plurality of striped source diffusions of a second conductivity type disposed within said semiconductor substrate between said striped drain diffusions;
• gate oxide deposited between said stripped drain diffusions and said striped source diffusions;
• a plurality of gate conductors at least partially overlying said gate oxide;
• isolation oxide deposited over said gate conductors;
• contact regions formed over said source and drain diffusions, said contact regions extending through said isolation oxide and at least partially exposing said source and drain diffusions;
• a plurality of first metal layer stripes, each associated with one of said source and drain diffusions, each at least partially overly said contact regions and electrically contacting said associated source and drain diffusion;
• a second isolation oxide overlying said first metal layer stripes;
• a plurality of second metal layer stripes, each overlying said first metal layer stripes and being perpendicular to said first metal layer stripes, each selectively electrically contacting either said source or drain diffusions to form source and drain busses;
• and
• a plurality of third metal layer conductors, each at least partially overlying said second layer stripes and being in electrical contact with an associated one of said second metal layer stripes to lower the resistance of said LDMOS transistor, said third metal layer conductors having a conductivity greater than the conductivity of the first and second metal layer stripes.

An LDMOS transistor, comprising:

• a plurality of striped diffusion regions of a first conductivity type defining source regions, the source regions being regular and being arranged in rows, the rows of source regions being further arranged in columns;
• a plurality of striped diffusion regions of a second conductivity type defining drain regions, the drain regions being rectangular and being arranged in rows disposed between said rows of source regions so that said row of drain regions and rows of source regions alternate in said columns;
• a plurality of gate oxide regions being formed around said rows of said source regions so the gate oxide regions are disposed between said alternating rows of drain and source regions in said columns;
• a plurality of gate polysilicon regions partially overlying each one of said plurality of gate oxide regions;
• a plurality of first metal regions forming source busses, each running perpendicular to said rows of said alternating source and drain regions, each running parallel to said columns, each source bus partially overlying said rows of source and drain regions;
• a plurality of second metal forming drain busses, each running perpendicular to said rows of said alternating source and drain regions, each running parallel to said columns, each drain bus partially overlying said rows of source and drain regions and being spaced apart from sold source busses and being disposed between them so that said source and drain busses alternate;
• and
• a plurality of copper third metal conductors overlying said second metal regions and electrically contacting said second metal regions to lower the resistance of said LDMOS transistor, said third metal layer conductors having a conductivity greater than the conductivity of the first and second metal layer regions.