Semiconductor integrated circuit device and method for manufacturing the same
AssigneeHitachi, Ltd.
InventorsSeiji Narui, Tetsu Udagawa, Kazuhiko Kajigaya, Makoto Yoshida
Life of this patent
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Abstract
The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q of a DRAM and a sheet resistance of bit lines BL.sub.1, BL.sub.2 are, respectively, 2 .OMEGA./.quadrature. or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL.sub.1, BL.sub.2 by which the number of the steps of manufacturing the DRAM can be reduced.
Claims18
A semiconductor integrated circuit device comprising:
- bit lines;
- word lines;
- memory cells each having a MISFET and a capacitor element coupled thereto, and each memory cell connected to one of said bit lines and one of said word lines,
- wherein each of said word lines comprises a polysilicon film, a first refractory metal film over said polysilicon film and a barrier metal film interposed between said polysilicon film and said first refractory metal film, and
- wherein each of said bit lines comprises a second refractory metal.
A semiconductor integrated circuit device comprising:
- bit lines each comprising a first W strip;
- word lines each comprising a polysilicon strip, a second W strip formed over said polysilicon strip and a barrier metal strip interposed between said polysilicon strip and said second W strip;
- and
- memory cells each having a MISFET including a gate electrode and source and drain regions, and a capacitor element coupled thereto, each memory cell being connected to one of bit lines and one of said word lines.
A semiconductor integrated circuit device o comprising:
- bit lines;
- word lines;
- and
- memory cells each having a MISFET and a capacitor element coupled thereto, and each memory cell connected to one of said bit lines and one of said word lines,
- wherein each of said word lines comprises a polysilicon film and a first refractory metal film over said polysilicon film and a barrier metal film between said polysilicon film and said refractory metal film,
- wherein each of said bit lines comprises a second refractory metal, and
- wherein said capacitor element is formed over one of said bit lines.
A semiconductor integrated circuit device comprising:
- bit lines each comprising a first W strip;
- word lines each comprising a polysilicon strip and a second W strip formed over said polysilicon strip and a barrier metal strip interposed between said polysilicon strip and said second W strip;
- and
- memory cells each having a MISFET including a gate electrode and source and drain regions, and a capacitor element coupled thereto, each memory cell connected to one of said bit lines and one of said word lines,
- wherein said bit lines are formed over said word lines and said capacitor element is formed over one of said bit lines.
Dependencies are inferred from the claim text.