US 6,150,688 AGranted

Semiconductor device and method of manufacturing the same

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsShigenobu Maeda, Yasuo Inoue, Hirotada Kuriyama, Shigeto Maegawa, Kyozo Kanamoto, Toshiaki Iwamatsu

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Abstract

A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

Claims17

Dependent claims

A semiconductor device in which contact is to be make at a deep position, comprising:

a substrate on which a dielectric layer and a semiconductor layer are formed successively;
a first impurity diffusion layer of a first conductivity type, which is disposed in said semiconductor layer and contains impurity of a first conductivity type implanted thereinto, said first impurity diffusion layer forming one of source/drain regions and forming said bit line;
a first interlayer insulating film disposed on said substrate and covering said first impurity diffusion layer;
a gate electrode disposed on said first interlayer insulating film, forming also said word line and having upper and lower surfaces;
a second interlayer insulating film disposed on said first interlayer insulating film and covering said gate electrode;
a contact hole penetrating said first interlayer insulating film, said gate electrode and said second interlayer insulating film and provided for exposing a portion of a surface of said first impurity diffusion layer;
a gate insulating film covering a side wall of said contact hole;
a first semiconductor layer of the first conductivity type formed in said contact hole, said first semiconductor layer being in contact with the surface of said first impurity diffusion layer and extending from the surface of said first impurity diffusion layer to the substantially same level as said lower surface of said gate electrode;
a second semiconductor layer of the first conductivity type and of the same conductivity type as said first semiconductor layer disposed in said contact hole, said second semiconductor layer being in contact with a surface of said first semiconductor layer and extending from the surface of said first semiconductor layer to the substantially same level as said upper surface of said gate electrode;
a third semiconductor layer of the first conductivity type disposed in said contact hole, said third semiconductor layer being in contact with a surface of said second semiconductor layer and disposed on said second semiconductor layer;
and
an interconnection connected to said third semiconductor layer.

9 more elements

A semiconductor device, which includes an AND circuit, comprising:

a substrate;
a first conductive layer of a first conductivity type disposed on said substrate;
a first interlayer insulating film disposed on said substrate and covering said first conductive layer;
a first gate electrode disposed on said first interlayer insulating film and having an upper surface and a lower surface;
a second interlayer insulating film disposed on said first interlayer insulating film and covering said first gate electrode;
a second gate electrode disposed on said second interlayer insulating film and having an upper surface and a lower surface;
a third interlayer insulating film disposed on said second interlayer insulating film and covering said second gate electrode;
a contact hole penetrating said first interlayer insulating film, said first gate electrode, said second interlayer insulating film, said second gate electrode and said third interlayer insulating film, and being provided for exposing a portion of a surface of said first conductive layer;
a gate insulating film covering side walls of said first and second gate electrodes exposed in said contact hole;
a first semiconductor layer of a first conductivity type formed in said contact hole, said first semiconductor layer being in contact with the surface of said first conductive layer and extending from the surface of said first conductive layer to the substantially same level as said lower surface of said first gate electrode;
a first channel semiconductor layer being formed in said contact hole, said first channel semiconductor layer being in contact with a surface of said first semiconductor layer and extending from the surface of said first semiconductor layer to the substantially same level as said upper surface of said first gate electrode;
a second channel semiconductor layer of a second conductivity type formed in said contact hole, and extending from said lower surface of said second gate electrode to the substantially same level as said upper surface of said second gate electrode;
and
a second semiconductor layer of the first conductivity type disposed on said second channel semiconductor layer, said second semiconductor layer being in contact with a surface of said second channel semiconductor layer and forming the other of said source/drain regions.

11 more elements

A semiconductor device, which includes an inverter circuit, comprising:

a first n.sup.+ -conductive layer;
a first interlayer insulating film disposed on said first n.sup.+ -conductive layer;
a first gate electrode disposed on said first interlayer insulating film and having an upper surface and a lower surface;
a second interlayer insulating film disposed on said first interlayer insulating film and covering said first gate electrode;
a first contact hole penetrating said first interlayer insulating film, said first gate electrode and said second interlayer insulating film, and provided for exposing a portion of a surface of said first n.sup.+ -conductive layer;
a first gate insulating film covering a side wall of said first contact hole;
a first n.sup.+ -semiconductor layer formed in said first contact hole, said first n.sup.+ -semiconductor layer being in contact with the surface of said first n.sup.+ -conductive layer and extending from the surface of said first n.sup.+ -conductive layer to the substantially same level as said lower surface of said first gate electrode;
a p.sup.- -semiconductor layer formed in said first contact hole, said p.sup.- -semiconductor layer being in contact with a surface of said first n.sup.+ -semiconductor layer and extending from the surface of said first n.sup.+ -semiconductor layer to the substantially same level as said upper surface of said first gate electrode;
a second n.sup.+ -semiconductor layer formed in said first contact hole and disposed on said p.sup.- -semiconductor layer, said second n.sup.+ -semiconductor layer being in contact with a surface of said p.sup.- -semiconductor layer and forming the other of said source/drain regions;
a second n.sup.+ -conductive layer disposed on said second interlayer insulating film and being in contact with said second n.sup.+ -conductive layer;
a first p.sup.+ -conductive layer disposed on said second n.sup.+ -conductive layer;
a third interlayer insulating film disposed on said first p.sup.+ -conductive layer;
a second gate electrode disposed on said third interlayer insulating film;
a fourth interlayer insulating film disposed on said third interlayer insulating film and covering said second gate electrode;
a second contact hole penetrating said fourth interlayer insulating film, said second gate electrode and said third interlayer insulating film, and provided for exposing a portion of a surface of said first p.sup.+ -conductive layer;
a second gate insulating film covering a side wall of said second contact hole;
a first p.sup.+ -semiconductor layer formed in said second contact hole, said first p.sup.+ -semiconductor layer being in contact with the surface of said first p.sup.+ -conductive layer and extending from the surface of said first p.sup.+ -conductive layer to the substantially same level as a lower surface of said second gate electrode;
an n.sup.- -semiconductor layer formed in said contact hole, said n.sup.- -semiconductor layer being in contact with a surface of said first p.sup.+ -semiconductor layer and extending from the surface of said first p.sup.+ -semiconductor layer to the substantially same level as an upper surface of said second gate electrode;
a second p.sup.+ -semiconductor layer formed in said contact hole and forming the other of said source/drain regions, said second p.sup.+ -semiconductor layer being disposed on said n.sup.- -semiconductor layer and being in contact with a surface of said n.sup.- -semiconductor layer;
and
a second p.sup.+ -conductive layer disposed on said fourth interlayer insulating film and being in contact with said second p.sup.+ -semiconductor layer.

18 more elements

A semiconductor device, which includes a flip-flop circuit, comprising:

a substrate;
a first conductive layer of a first conductivity type disposed on said substrate;
a first interlayer insulating film disposed on said substrate and covering said first conductive layer;
a first gate electrode of the first conductivity type disposed on said first interlayer insulating film and having an upper surface and a lower surface;
a second interlayer insulating film disposed on said first interlayer insulating film and covering said first gate electrode;
a first contact hole penetrating said first interlayer insulating film, said first gate electrode and said second interlayer insulating film, and provided for exposing a portion of a surface of said first conductive layer;
a first gate insulating film covering a side wall of said first contact hole;
a first semiconductor layer of a first conductivity type formed in said first contact hole, said first semiconductor layer being in contact with a surface of said first conductive layer and extending from the surface of said first conductive layer to the substantially same level as said lower surface of said first gate electrode;
a first channel semiconductor layer of a second conductivity type formed in said first contact hole, said first channel semiconductor layer being in contact with a surface of said first semiconductor layer and extending from the surface of said first semiconductor layer to the substantially same level as said upper surface of said first gate electrode;
a second semiconductor layer of the first conductivity type formed in said first contact hole and forming the other of said source/drain regions, said second semiconductor layer being disposed on said first channel semiconductor layer and being in contact with the surface of said first channel semiconductor layer;
a second gate electrode of the first conductivity type disposed on said second interlayer insulating film and being in contact with said second semiconductor layer;
a third interlayer insulating film disposed on said second interlayer insulating film and covering said second gate electrode;
a second contact hole penetrating said third interlayer insulating film, said second gate electrode and said second interlayer insulating film, and provided for exposing a portion of a surface of said first gate electrode;
a second gate insulating film covering a side wall of said second contact hole;
a third semiconductor layer of the first conductivity type formed in said second contact hole, said third semiconductor layer being in contact with a surface of said first gate electrode and extending from the surface of said first gate electrode to the substantially same level as said lower surface of said second gate electrode;
a second channel semiconductor layer of the second conductivity type formed in said second contact hole, said second channel semiconductor layer being in contact with a surface of said third semiconductor layer and extending from the surface of said third semiconductor layer to the substantially same level as an upper surface of said second gate electrode;
a fourth semiconductor layer of the first conductivity type formed in said second contact hole and disposed on said second channel semiconductor layer, said fourth semiconductor layer being in contact with a surface of said second channel semiconductor layer and forming the other of said source/drain regions;
and
a second conductive layer of the first conductivity type disposed on said third interlayer insulating film and connected to said fourth semiconductor layer.

16 more elements

A semiconductor device, which includes an AND circuit, comprising:

a substrate;
a first conductive layer of a first conductivity type disposed on said substrate;
a first interlayer insulating film disposed on said substrate and covering said first conductive layer;
a first gate electrode disposed on said first interlayer insulating film and having an upper surface and a lower surface;
a second interlayer insulating film disposed on said first interlayer insulating film and covering said first gate electrode;
a second gate electrode disposed on said second interlayer insulating film and having an upper surface and a lower surface;
a third interlayer insulating film disposed on said second interlayer insulating film and covering said second gate electrode;
a contact hole penetrating said first interlayer insulating film, said first gate electrode, said second interlayer insulting film, said second gate electrode and said third interlayer insulating film, having a bottom portion spreading radially outward, and being provided for exposing a portion of a surface of said first conductive layer;
a first semiconductor layer of a first conductivity type formed in said contact hole, said first semiconductor layer being in contact with the surface of said first conductive layer and extending from the surface of said first conductive layer to the substantially same level as said lower surface of said first gate electrode;
a first channel semiconductor layer being formed in said contact hole, said first channel semiconductor layer being in contact with a surface of said first semiconductor layer and extending from the surface of said first semiconductor layer to the substantially same level as said upper surface of said first gate electrode;
a second channel semiconductor layer of a second conductivity type formed in said contact hole, and extending from said lower surface of said second gate electrode to the substantially same level as said upper surface of said second gate electrode;
a second semiconductor layer of the first conductivity type disposed on said second channel semiconductor layer, said second semiconductor layer being in contact with a surface of said second channel semiconductor layer and forming the other of said source/drain regions;
a first gate insulating film provided between said first gate electrode and said first channel semiconductor layer, and
a second gate insulating film provided between said second gate electrode and said second channel semiconductor layer

11 more elements

A semiconductor device, which includes an inverter circuit, comprising:

a first n.sup.+ -conductive layer;
a first interlayer insulating film disposed on said first n.sup.+ -conductive layer;
a first gate electrode disposed on said first interlayer insulating film and having an upper surface and a lower surface;
a second interlayer insulating film disposed on said first interlayer insulating film and covering said first gate electrode;
a first contact hole penetrating said first interlayer insulating film, said first gate electrode and said second interlayer insulating film, having a bottom portion spreading radially outward, and provided for exposing a portion of a surface of said first n.sup.+ -conductive layer;
a first n.sup.+ -semiconductor layer formed in said first contact hole, said first n.sup.+ -semiconductor layer being in contact with the surface of said first n.sup.+ -conductive layer and extending from the surface of said first n.sup.+ -conductive layer to the substantially same level as said lower surface of said first gate electrode;
a p.sup.- - semiconductor layer formed in said first contact hole, said p.sup.+ semiconductor layer being in contact with a surface of said first n.sup.+ -semiconductor layer and extending from the surface of said first n.sup.+ -semiconductor layer to the substantially same level as said upper surface of said first gate electrode;
a second n.sup.+ -semiconductor layer formed in said first contact hole and disposed on said p.sup.- -semiconductor layer, said second n.sup.+ -semiconductor layer being in contact with a surface of said p.sup.- -semiconductor layer and formed the other of said source/drain regions;
a first gate insulating film provided between said first gate electrode and p.sup.- -semiconductor layer;
a second n.sup.+ -conductive layer disposed on said second interlayer insulating film and being in contact with said second n.sup.+ -conductive layer;
a first p.sup.+ -conductive layer disposed on said second n.sup.+ -conductive layer;
a third interlayer insulating film disposed on said first p.sup.+ -conductive layer;
a second gate electrode disposed on said third interlayer insulating film;
a fourth interlayer insulating film disposed on said third interlayer insulating film and covering said second gate electrode;
a second contact hole penetrating said fourth interlayer insulating film, said second gate electrode and said third interlayer insulating film, having a bottom portion spreading radially outward, and provided for exposing a portion of a surface of said first p.sup.+ - conductive layer;
a first p.sup.+ -semiconductor layer formed in said second contact hole, said first p.sup.+ -semiconductor layer being in contact with the surface of said first p.sup.+ -conductive layer and extending from the surface of said first p.sup.+ -conductive layer to the substantially same level as a lower surface of said second gate electrode;
an n.sup.- -semiconductor layer formed in said second contact hole, said n.sup.- -semiconductor layer being in contact with a surface of said first p.sup.+ -semiconductor layer and extending from the surface of said first p.sup.+ -semiconductor layer to the substantially same level as an upper surface of said second gate electrode;
a second p.sup.+ semiconductor layer formed in said second contact hole and forming the other of said source/drain regions, said second p.sup.+ -semiconductor layer being disposed on said n.sup.- -semiconductor layer and being in contact with a surface of said n.sup.- -semiconductor layer;
a second p.sup.+ -conductive layer disposed on said fourth interlayer insulating film and being in contact with said second p.sup.+ -semiconductor layer, and
a second gate insulating film provided between said second gate electrode and n.sup.- -semiconductor layer.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/038,981Filed 12 Mar 1998 · division
Priority: JP 6-11299726 May 1994
Granted: 21 Nov 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 12/34
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: the transistor being at least partially in a trench in the substrate
H10B 12/395
The capacitor and the transistor being in a same trench: the transistor being vertical
H10D 30/6728
Thin-film transistors [TFT]: vertical TFTs
H10D 86/01
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…

Family

Serial313,472Parent of this continuation · filed 27 Sep 1994
Serial648,828Parent of this division · filed 16 May 1996
Serial758,841Parent of this division · filed 2 Dec 1996
US 5,780,888 AParent of this division
US 5,627,390 AParent of this division
US 6,150,688 AThis patent

From the US filing history. Foreign family members aren’t listed.