US 6,150,679 A · FIFO architecture with built-in intelligence for use in a graphics memory system for reducing paging overhead

Abstract

The present invention provides a first-in-first-out (FIFO) memory device comprising a first latch array, a second latch array, a write pointer device, a first read pointer device, and a second read pointer device. Preferably, the FIFO memory device of the present invention is implemented in a graphics memory system having a two-bank architecture for reducing paging overhead. The second latch array is used for storing row addresses for bank0 and bank1 of the frame buffer memory of the graphics memory system. The first latch array is used for storing column addresses and any other related data for bank0 and bank1 of the frame buffer memory. When the row addresses are loaded into the second latch array, the row addresses are tagged with a bank bit that indicates which bank the row address will access. Additionally, row addresses that require re-paging of either bank0 or bank1 are tagged with a paging bit. The second read pointer device determines which of the row addresses has been tagged with a paging bit to determine which row addresses are candidates for bank0 and bank1 transactions. The second read pointer device then prioritizes the bank0 candidates and the bank1 candidates to determine which of the bank0 candidates is a dump candidate and which of the bank1 candidates is a dump candidate. The second read pointer device then prioritizes the dump candidates and selects the row address corresponding to the dump candidate that was loaded first and that will be required first. This row address is then sent to a row port output register. Once this row address has been unloaded from the row port output register, the row address corresponding to the next dump candidate can then be sent to the row port output register. This aspect of the present invention allows a row address for one bank to be loaded into the row port output register while transactions for the other bank are being processed, thus allowing re-paging to be "hidden".

Claims11

Dependent claims

a first-in-first-out (FIFO) memory device comprising:

a first memory element, the first memory element receiving a first set of entries from an input port of the FIFO memory device and storing each of the entries of the first set in a storage location in the first memory element addressed by a write pointer device;
a second memory element, the second memory element receiving a second set of entries from the input port of the FIFO memory device and storing each of the entries of the second set in a storage location in the second memory element addressed by the write pointer device;
a first read pointer device, the first read pointer device determining first read pointer addresses in the first memory element, the first read pointer addresses being used to address storage locations in the first memory element for reading entries of the first set of entries out of storage locations in the first memory element, the entries read out of the first memory element being output from the FIFO memory device via a first output port of the FIFO memory device;
and
a second read pointer device, the second read pointer device determining whether any of the entries of the second set are tagged entries, the second read pointer device calculating second read pointer addresses based on any tagged entries in the second set, the second read pointer device using the second read pointer addresses for reading the tagged entries of the second set out of their respective storage locations in the second memory element, the tagged entries read out of the second memory element being output from the FIFO memory device via a second output port of the FIFO memory device.

2 more elements

Dependencies are inferred from the claim text.

FIFO architecture with built-in intelligence for use in a graphics memory system for reducing paging overhead

Life of this patent

FIFO architecture with built-in intelligence for use in a graphics memory system for reducing paging overhead

Life of this patent

Abstract

Claims11