Method for fabricating metal-oxide semiconductor transistor
AssigneeUnited Semiconductor Corp.
InventorsClaymens Lee, Gary Hong
Life of this patent
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Abstract
A method for fabricating a metal-oxide semiconductor (MOS) transistor on a semiconductor substrate is described. The invention introduces an air chamber with a low dielectric constant between the gate and the source/drain region so as to lower the fringing electric field between the gate and the source/drain region. Moreover, the dielectric constant of the dielectric layer between the gate and the source/drain region is reduced. Therefore, the gate-to-drain capacitance is decreased in the MOS transistor.
Claims12
A method for fabricating a metal-oxide semiconductor (MOS) transistor, comprising:
- providing a semiconductor substrate, wherein a gate is formed on the substrate, and a first doped region is formed in the substrate beside the gate;
- forming a first dielectric layer with a first thickness on the substrate beside the gate, the first dielectric layer having a first surface level lower than that of the gate;
- forming a first spacer on a sidewall of the gate;
- anisotropically etching a part of the first dielectric layer until the first dielectric layer having a second surface level lower than the first surface level, with the gate and the first spacer serving as a mask;
- forming a second spacer to cover the first spacer and a part of the first dielectric layer;
- anisotropically etching the first dielectric layer to expose the substrate, with the second spacer and the gate serving as a mask;
- forming a second doped region in the substrate with the second spacer and the gate serving as a mask, wherein the first and the second doped regions form a source/drain region;
- removing the remaining first dielectric layer;
- and
- forming a second dielectric layer to cover the gate.
A method for fabricating a metal-oxide semiconductor (MOS) transistor, comprising:
- providing a semiconductor substrate, wherein a gate is formed on the substrate, and a first doped region is formed in the substrate beside the gate;
- forming a first dielectric layer with a first thickness on the substrate beside the gate, the first thickness of the first dielectric layer is smaller than a thickness of the gate, so that the first dielectric layer covers a part of a sidewall of the gate;
- forming a first spacer on an exposed sidewall of the gate;
- anisotropically etching a part of the first dielectric layer until the first dielectric layer with a second thickness, with the gate and the first spacer serving as a mask, wherein the second thickness is smaller than the first thickness;
- forming a second spacer to cover the first spacer and a part of the first dielectric layer;
- anisotropically etching the first dielectric layer to expose the substrate with the second spacer and the gate serving as a mask;
- removing the remaining first dielectric layer;
- and
- forming a second dielectric layer to cover the gate so that an air chamber is formed under the first and the second spacers.
Dependencies are inferred from the claim text.