US 6,150,256 A · Method for forming self-aligned features

Abstract

The present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that the lower resist is exposed only where an opening has been formed in the upper resist layer. This self-aligning enables the vias to be printed as elongated shapes, which allows for the use of particularly effective image enhancement techniques. The invention further provides a simplified procedure for creating vias and trenches, in that only one etch step is required to simultaneously create both vias and trenches. An alternative embodiment of the invention allows looped or linked images, such as those printed using image enhancement techniques, to be trimmed to form isolated features.

Claims53

Dependent claims

A method for defining a feature on a substrate, the method comprising the steps of:

(A) applying a lower photoresist layer over the substrate;
(B) applying an upper photoresist layer over the lower photoresist layer;
(C) exposing the upper photoresist layer through a first mask;
(D) developing the upper photoresist layer, such that openings are formed in the upper photoresist layer;
(E) exposing the lower photoresist layer through a second mask and through the upper photoresist openings, such that the portions of the lower photoresist layer corresponding to the intersection of the upper photoresist openings and the corresponding openings in the second mask are exposed;
(F) developing the lower photoresist layer, such that openings are formed in the lower photoresist layer;
and
(G) forming the feature using the lower photoresist openings.

5 more elements

A method for forming self-aligned wires and interconnects on a semiconductor substrate, the method comprising the steps of:

(A) forming a dielectric layer over the surface of the substrate;
(B) applying a lower photoresist layer over the dielectric layer;
(C) applying an upper photoresist layer over the lower photoresist layer;
(D) patterning the wires by:
(i) exposing the upper photoresist layer to light of a first wavelength to which the upper photoresist layer responds through a first mask having a first exposure pattern, such that only portions of the upper photoresist layer corresponding to the first exposure pattern receive the light of the first wavelength;
and
(ii) developing the upper photoresist layer, such that openings are formed in the upper photoresist layer;
(E) patterning the interconnects by:
(i) exposing the lower photoresist layer to light of a second wavelength to which the lower photoresist layer responds through a second mask having a second exposure pattern and through the openings of the upper photoresist layer, such that only the portions of the lower photoresist that underlay an opening of the upper photoresist layer and correspond to the second exposure pattern receive the light of the second wavelength;
and
(ii) developing the lower photoresist layer such that openings are formed in the lower photoresist layer where the lower photoresist layer received light of the second wavelength;
(F) etching trenches in the dielectric layer in locations corresponding to the openings in the upper photoresist layer;
(G) etching vias through the dielectric layer in locations corresponding to the openings in the lower photoresist layer;
(H) overfilling the surface of the substrate with a metal, such that the trenches and vias are filled with the metal;
and
(I) planarizing the metal such that the metal remains only in the vias and the trenches.

13 more elements

Dependencies are inferred from the claim text.

Method for forming self-aligned features

Life of this patent

Method for forming self-aligned features

Life of this patent

Abstract

Claims53