Method for fabricating MOS transistor having raised source and drain

A process of fabricating on a substrate a semiconductor device having a raised source, a raised drain and a gate electrode structure, comprising the steps of:

• forming a plurality of isolation regions on said substrate to isolate a plurality of active regions;
• forming on one of said active regions a gate electrode structure;
• depositing sequentially a first dielectric layer and a second dielectric layer on said substrate and said gate electrode structure;
• removing a top portion of said second dielectric layer to expose a portion of said first dielectric layer covering said gate electrode structure;
• forming on said substrate a patterned resist layer to mask portions of said second dielectric layer;
• removing said second dielectric layer other than said portions masked by said resist layer to form a plurality of trenches adjacent to said gate electrode structure, wherein portions of the substrate are exposed, and wherein spacers are formed on sidewalls of the gate electrode structure at the same time;
• filling said plurality of trenches with a first conductor layer;
• doping said first conductor layer in the trenches with dopants;
• and
• driving said dopants into portions of said substrate underneath said trenches to form said raised source and said raised drain.

A semiconductor device having a raised source, a raised drain and a gate electrode structure, fabricated on a substrate by a process comprising the steps of:

• forming a plurality of isolation regions on said substrate to isolate a plurality of active regions;
• forming sequentially a first dielectric layer, a first conductor layer and a second dielectric layer on said substrate;
• forming on one of said active regions a patterned first resist layer to mask a portion of said second dielectric layer and the underlying first conductor layer and first dielectric layer;
• removing said second dielectric layer, said first conductor layer and said first dielectric layer other than said portion masked by said first resist layer to form said gate electrode structure;
• depositing sequentially a third dielectric layer and a fourth dielectric layer on said substrate and said gate electrode structure;
• planarizing a top portion of said fourth dielectric layer to expose a portion of said third dielectric layer covering said gate electrode structure;
• forming on the substrate a patterned second resist layer to mask portions of the fourth dielectric layer;
• removing said fourth dielectric layer other than said portions masked by said second resist layer to form a plurality of trenches adjacent to said gate electrode structure, wherein portions of the substrate are exposed, and wherein spacers are formed on sidewalls of the gate electrode structure at the same time;
• filling said plurality of trenches with a second conductor layer;
• doping said second conductor layer in the trenches with dopants;
• and
• driving said dopants into the substrate underneath said trenches to form said raised source and said raised drain.