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US 6,150,232 AGranted
Formation of low k dielectric
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsLap Chan, Cher Liang Cha, Kok Keng Ong, Kheng Chok Tee
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Abstract
A method for creating low intra-level dielectric interface between conducting lines using conventional deposition and etching processes. A layer of conducting lines is formed interspersed with dielectric material. A dummy, high-density pattern of low k dielectric material is created on top of this layer. The dielectric material between the metal lines is removed. The dummy high-density pattern is interconnected, deposited on top of this interconnected layer is a low k dielectric to form an inter layer dielectric.
Claims54
A method for forming a physical structure, comprising:
- securing a semiconductor substrate in which a base layer is formed;
- forming a pattern of photo resist on top of said semiconductor substrate said pattern being the mirror image of the desired conducting line pattern on top of said semiconductor substrate thereby forming an intra-level pattern of photoresist;
- forming said desired conducting line pattern said desired conducting line pattern being formed within the spaces or holes within said intra-level pattern of photoresist said desired conducting line pattern further being within the plane of said intra-level pattern of photoresist thereby forming a layer of conducting line pattern and intra-level pattern of photoresist;
- planarizing the top surface of said layer of conducting line pattern and intra-level pattern of photoresist;
- forming a high density pattern of low dielectric constant material overlaying said layer of conducting line pattern and intra-level pattern of photoresist;
- forming intra-level air gaps within said layer of conducting line pattern and intra-level pattern of photoresist thereby forming a layer of conducting line pattern and intra-level air gaps;
- closing the gaps within said high density pattern of low dielectric constant material to form a low dielectric constant layer on top of said layer of conducting line pattern and intra-level air gaps;
- and
- depositing an inter-level dielectric on top of said low dielectric constant layer.
6 more elements
A method for forming air gaps between conducting lines of a semiconductor device, comprising the steps of:
- securing a semiconductor substrate in which a base layer is formed;
- depositing a photo resist layer on said base layer;
- etching said photo resist layer into a photo resist pattern that is the mirror image of the pattern of the metal leads that are to be formed on top of said substrate base layer, said photo resist pattern having tops and sidewalls with a spacing or gap between said photo resist pattern, wherein portions of said substrate base are being exposed in the areas of said gaps between said photo resist pattern;
- depositing a metal layer on top of said photo resist pattern and on top of said exposed portions of said substrate base;
- planarizing said metal layer down to the level of the top of said deposited photo resist pattern thereby obtaining a top surface of said pattern of photo resist and of conducting lines within said pattern of photo resist;
- securing a dummy mask that exhibits a pattern of openings;
- positioning said dummy mask such that said dummy mask partially blocks said top surface from exposure to a source of material deposition;
- depositing low k dielectric material on top of said top surface such that said mask partially intercepts the deposition of the low k dielectric material thereby forming a pattern of low-k high density dielectric material on said top surface;
- removing said deposited photo resist pattern thereby forming intra-level air gaps in the plane of said conducting lines;
- closing the openings within said pattern of low-k high density dielectric material thus forming a low-k intra-level dielectric base layer;
- and
- depositing a layer of low k dielectric material on top of said low k intra-level dielectric thereby forming a low-k interlevel dielectric layer.
9 more elements
A method for forming air gaps between conducting lines of a semiconductor device, comprising the steps of:
- securing a semiconductor substrate in which a base layer is formed;
- depositing a metal layer on said base layer;
- etching said metal layer into a pattern of conductive leads wherein said conductive leads having tops and sidewalls with a spacing or gap between said conductive leads, wherein portions of said substrate base layer are being exposed in the areas of said gaps between said conductive leads pattern;
- depositing a photo resist layer on top of said pattern of conductive leads and on top of said exposed portions of said substrate base;
- planarizing said photo resist layer down to the level of the top of said conductive leads thereby obtaining a top surface of said pattern of photo resist and of said conductive leads within said pattern of photo resist;
- depositing a layer of low-k high mechanical strength dielectric material on the surface of said pattern of photo resist and conductive leads;
- securing a dummy mask that exhibits a pattern of openings;
- positioning said dummy mask such that said dummy mask partially blocks said top surface of said pattern of photo resist and conductive leads;
- etching said low-k high mechanical strength dielectric material on the surface of said pattern of photo resist and conductive leads such that said mask partially inhibits said etching thereby forming a low-k high density dielectric pattern on top of said surface;
- removing said deposited photo resist from said pattern of photo resist and conductive leads thereby forming intra-level air gaps;
- closing the openings within said low-k high density dielectric pattern thus forming a low-k inter-level dielectric base layer;
- and
- depositing a layer of low k dielectric material on top of said low k inter-level dielectric thereby forming a low-k interlevel dielectric layer.
10 more elements
Dependencies are inferred from the claim text.