Semiconductor device and method for manufacturing same
AssigneeNEC Corporation
InventorTohru Aoyama
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Abstract
It is an object of the invention to provide a CMOS device comprising p-channel FETs having shallow source and drain regions and a method for fabricating the same. A B-doped selective epitaxial layer is grown only on an area, where the source and drain regions of the p-channel FET is to be formed. Growth of the B-doped selective epitaxial layer on an area, where the source and drain regions of a n-channel FET is to be formed, is impeded by forming a amorphous region on the area corresponding to the n-channel FET.
Claims26
A method for fabricating a CMOS device comprising:
- forming an insulator layer on a surface of a substrate,
- forming gate electrodes on said insulator layer,
- forming side walls surrounding said gate electrodes,
- exposing only areas surrounding said gate electrodes on said surface of said substrate, where n-type ions are to be implanted, by processing photoresist,
- implanting said n-type impurity ions on said exposed areas on said surface of said substrate,
- amorphizing said exposed areas on said surface of said substrate to inhibit growth of p-type impurity doped epitaxial layers,
- growing p-type impurity doped selective epitaxial layers on areas surrounding said side walls on said surface of said substrate, where p-type impurity ions are to be doped, and
- forming source and drain regions by diffusing said p-type impurity into said surface of said substrate from said p-type impurity doped selective epitaxial layer.
A method for fabricating a CMOS device comprising:
- forming an insulator layer on a surface of a substrate,
- forming gate electrodes on said insulator layer,
- forming side walls surrounding said gate electrodes,
- exposing only areas surrounding said gate electrodes on said surface of said substrate, where n-type impurity ions are to be implanted, by processing photoresists,
- implanting n-type impurity ions on said exposed areas,
- introducing dry etching defects to said exposed areas on said surface of said substrate to inhibit growth of p-type impurity doped epitaxial layers,
- growing p-type impurity doped selective epitaxial layers on areas surrounding said side walls on said surface of said substrate, where p-type impurity ions are to be doped, and
- forming source and drain regions by diffusing said p-type impurity into said surface of said substrate from said p-type impurity doped selective epitaxial layers.
A method of fabricating a semiconductor device, comprising:
- forming gate electrodes with corresponding insulating side walls and insulating portions for at least one n-type FET and for at least one p-type FET;
- selectively implanting n-type impurities in a first subset of source/drain regions corresponding to said at least one n-type FET;
- selectively treating said first subset of source/drain regions to inhibit growth of a semiconductor layer containing p-type impurities;
- selectively growing said layer containing p-type impurities on a second subset of source/drain regions corresponding to said at least one p-type FET, wherein said layer does not grow on said first region;
- and
- causing p-type impurities to be diffused into said second subset of source/drain regions.
Dependencies are inferred from the claim text.