Leakage current reduction of a tantalum oxide layer via a nitrous oxide high density annealing procedure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShi-Chung Sun, Jiann-Shing Lee
Life of this patent
Estimating the term…
Abstract
A process of fabricating a capacitor structure, using a tantalum oxide capacitor dielectric layer, has been developed. The process features deposition of a thin, high dielectric constant tantalum oxide layer, followed by a high density plasma anneal procedure, used to reduce the leakage current in the as-deposited tantalum oxide layer, that can evolve during normal operating conditions of the capacitor structure. The high density plasma anneal procedure is performed in a nitrous oxide ambient, at a temperature of about 400.degree. C.
Claims16
A method of fabricating a capacitor structure, on a semiconductor substrate, comprising the steps of:
- providing a planarized conductive plug structure, in a storage node contact hole, located in an insulator layer, with the conductive plug structure contacting a source/drain region of a transfer gate transistor;
- forming a storage node structure, overlying the top surface of said insulator layer, and overlying and contacting, the top surface of said conductive plug structure;
- forming a tantalum oxide capacitor dielectric layer directly on said storage node structure;
- performing a plasma anneal procedure, in an oxygen containing ambient, at a temperature between about 400 to 450.degree. C.;
- and
- forming an upper electrode structure.
A method of fabricating a capacitor structure for a dynamic random access memory, (DRAM), device, featuring a nitrous oxide anneal procedure, performed after deposition of a tantalum oxide capacitor dielectric layer, comprising the steps of:
- forming a storage node contact hole, in an insulator layer, exposing a portion of the top surface of a source/drain region, of a transfer gate transistor;
- forming a planarized polysilicon plug structure, in said storage node contact hole;
- forming a polysilicon storage node structure with a top surface of said polysilicon storage node structure comprised with hemispherical grain silicon, and with a portion of said polysilicon storage node structure, overlying and contacting said polysilicon plug structure;
- depositing said tantalum oxide capacitor dielectric layer directly on hemispherical grain silicon surface, of polysilicon storage node structure;
- performing said nitrous oxide anneal procedure, in a plasma, at a temperature between about 400 to 450.degree. C., to create an annealed tantalum oxide capacitor dielectric layer;
- and
- forming a polysilicon upper electrode structure, on said annealed tantalum oxide capacitor dielectric layer.
Dependencies are inferred from the claim text.