Method for fabricating a crown capacitor with rough surface

A method for fabricating a crown capacitor with a rough surface on a substrate having a semiconductor source diffusion region comprising the steps of:

• forming a first- conducting layer which contacts the semiconductor source diffusion region on the substrate;
• forming a first insulating layer on the first conducting layer to form a stacked layer comprising the first insulating layer and the first conducting layer;
• defining the stacked layer to form a residue portion of the stacked layer adjacent to the semiconductor source diffusion region;
• forming a second conducting layer conformably on the substrate and the stacked layer;
• etching back the second conducting layer to form first conducting spacers adjacent to side-walls of the stacked layer;
• forming a third conducting layer having a rough surface conformably on the substrate, the first conducting spacers, and the stacked layers;
• forming a second insulating layer conformably on the third conducting layer having the rough surface;
• etching back the second insulating layer and the third conducting layer having a rough surface to form second conducting spacers having a rough surface adjacent to the first conducting spacers, and third insulating spacers adjacent to the second conducting spacers;
• removing the first insulating layer and the third insulating spacers to form a storage-node capacitor plate composed of the first conducting spacers, the second conducting spacers, and the first conducting layer;
• forming a dielectric layer on the storage-node capacitor plate;
• and
• forming an upper plate on the dielectric layer.

A method for fabricating a crown capacitor with a rough surface on a substrate having a semiconductor source diffusion region comprising the steps of:

• forming a first BPSG layer on the substrate;
• forming an etching stop layer on the first BPSG layer;
• defining the etching stop layer and the first BPSG layer to form an opening exposing the semiconductor source diffusion region;
• forming a first doped polycrystalline silicon layer filled into the opening which contacts the semiconductor source diffusion region on the etching stop layer;
• forming a second BPSG layer on the first doped polycrystalline silicon layer to form a stacked layer;
• defining the stacked layer to form a residue portion of the stacked layer adjacent to the semiconductor source diffusion region;
• forming a second doped polycrystalline silicon layer conformably on the etching stop layer and the stacked layer,
• etching back the second doped polycrystalline silicon layer to form a first conducting spacers composed of the doped polycrystalline silicon layer adjacent to side-walls of the stacked layer;
• forming a polycrystalline silicon layer having a rough surface conformably on the etching stop layer, the first conducting spacers, and the stacked layers;
• forming a non doped silicon glass conformably on the polycrystalline silicon layer with the rough surface,
• etching back the non doped silicon glass and the polycrystalline silicon layer having a rough surface to form second conducting spacers having a rough surface adjacent to the first conducting spacers, and third insulating spacers composed of non doped silicon glass adjacent to the second conducting spacers with the rough surface;
• removing the second BPSG layer and the third insulating spacers to form a storage-node capacitor plate composed of the first conducting spacers, the second conducting spacers with the rough surface, and the first doped polycrystalline silicon layer;
• forming a dielectric layer on the storage-node capacitor plate;
• and
• forming an upper plate on the dielectric layer.