US 6,150,206 A · Methods of forming integrated circuit capacitors using trench isolation and planarization techniques

Abstract

Methods of forming integrated circuit capacitors include the steps of forming a trench in a first electrically insulating layer and then forming a first electrically conductive layer on a sidewall and bottom of the trench. A dielectric layer is then formed on the first electrically conductive layer. Next, a second electrically conductive layer is formed on the dielectric layer, opposite the first electrically conductive layer. A step is then performed to planarize the first and second electrically conductive layers to define first and second electrodes of a capacitor in the trench. In particular, the step of planarizing the first electrically conductive layer comprises planarizing the first electrically conductive layer to define a first electrode having a U-shaped cross-section. This step results in the formation of a first electrode having a relatively large effective area (which is a function of the depth of the trench) for a given lateral dimension.

Claims14

Dependent claims

A method of forming an integrated circuit capacitor, comprising the steps of:

forming a first electrically insulating layer on a semiconductor substrate;
forming a recess in the first electrically insulating layer;
forming a contact hole which expose the semiconductor substrate, in the first electrically insulating layer;
forming a first electrically conductive layer on a sidewall and bottom of the recess and in the contact hole;
forming a dielectric layer on the first electrically conductive layer;
forming a second electrically conductive layer, on the dielectric layer;
opposite the first electrically conductive layer;
planarizing the first and second electrically conductive layers simultaneously to define first and second capacitor electrodes in the recess and define a conductive plug in the contact hole that is electrically disconnected from the first capacitor electrode;
and then
forming a first wiring layer which electrically connects the conductive plug to the first capacitor electrode, on the first electrically insulating layer.

7 more elements

A method of forming an integrated circuit capacitor, comprising the steps of:

forming a first electrically insulating layer on a face of a semiconductor substrate;
forming a first mask on the first electrically insulating layer;
selectively etching the first electrically insulating layer to define a recess therein, using a first mask as an etching mask;
forming a second mask on the first electrically insulating layer;
selectively etching the first electrically insulating layer to define a contact hole therein which exposes the face of the semiconductor substrate, using the second mask as an etching mask;
forming a first electrically conductive layer in the contact hole and in the recess;
forming a dielectric layer on the first electrically conductive layer;
forming a second electrically conductive layer on the dielectric layer, opposite the first electrically conductive layer;
planarizing the first and second electrically conductive layers simultaneously to define first and second capacitor electrodes in the recess and define an electrically conductive plug in the contact hole that is electrically disconnected from the first capacitor electrode;
and then
forming a first wiring layer which electrically connects the electrically conductive plug to the first capacitor electrode, on the first electrically insulating layer.

8 more elements

Dependencies are inferred from the claim text.

Methods of forming integrated circuit capacitors using trench isolation and planarization techniques

Life of this patent

Methods of forming integrated circuit capacitors using trench isolation and planarization techniques

Life of this patent

Abstract

Claims14