US 6,150,073 AGranted

Degradation-free low-permittivity dielectrics patterning process for damascene

AssigneeUnited Microelectronics Corp.

InventorYimin Huang

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Abstract

A degradation-free, low-permittivity dielectrics patterning process for damascene starts with provision of a substrate, wherein the substrate has a dielectric layer and a via plug formed on it. Then, a inter-metal dielectric layer and an insulating layer are formed in sequence on the dielectric layer. A hard mask layer is next formed on the insulating layer, and is subsequently patterned. An etching process is performed on the insulating layer and the inter metal dielectric layer by using the patterned hard mask layer as a mask to form a metal line trench and expose the via plug. The metal line trench is then filled with metal by forming a metal layer on the hard mask layer. A metal line in the shallow trench is formed by performing chemical mechanical polishing on the metal layer to expose the insulating layer, and then performing post-chemical mechanical polishing cleaning.

Claims36

Dependent claims

A degradation-free, low-permissivity dielectric patterning process for damascene, the process comprising:

providing a substrate, wherein the substrate has a dielectric layer and a via plug formed on it;
forming an inter-metal dielectric layer on the dielectric layer, wherein the inter-metal dielectric layer has a thickness;
forming an insulating layer on the inter-metal dielectric layer for protecting the inter-metal dielectric layer from being damaged by a photoresist removal process and a post-chemical mechanical polishing cleaning process, wherein the insulating layer has a thickness and the insulating layer is thinner than the inter-metal dielectric layer;
forming a hard mask layer on the insulating layer, wherein the hard mask layer has a thickness;
forming and patterning a photoresist layer on the hard mask layer to expose a portion of the hard mask layer;
performing an etching process on the hard mask layer until the insulating layer is exposed to form a shallow trench;
performing oxygen plasma ashing and wet chemical cleaning to remove the photoresist layer;
performing an etching process on the insulating layer and the inter-metal dielectric layer by using the hard mask layer as a mask to form a metal line trench and expose the via plug;
forming a glue/barrier layer conformal to the metal line trench and the hard mask layer;
forming a metal layer on the glue/barrier layer to fill the metal line trench;
performing chemical mechanical polishing on the metal layer to expose the insulating layer and form a metal line in the shallow trench, wherein the metal line is electrically connected to the via plug;
and
performing post-chemical mechanical polishing cleaning.

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Dependencies are inferred from the claim text.